Buried bit line anti-fuse one-time-programmable nonvolatile memory

Abstract

An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P.sup.−doped regions. Another N.sup.+doped region, functioning as a bit line, is positioned adjacent and between the two P.sup.−doped regions on the substrate. An anti-fuse is defined over the N.sup.+doped region. Two insulator regions are deposited over the two P.sup.−doped regions. An impurity doped polysilicon layer is defined over the two insulator regions and the anti-fuse. A polycide layer is defined over the impurity doped polysilicon layer. The polycide layer and the polysilicon layer function as a word line. A programmed region, i.e., a link, functioning as a diode, is formed on the anti-fuse after the anti-fuse OTP nonvolatile memory cell is programmed. The array structure of anti-fuse OTP nonvolatile memory cells and methods for programming, reading, and fabricating such a cell are also disclosed.

Dependencies are inferred from the claim text.