Reducing wafer distortion through a low CTE layer

A method of fabricating a semiconductor device, comprising:

• providing a first silicon substrate having opposite first and second sides, the first and second sides including a first silicon (111) surface and a second silicon (111) surface, respectively;
• forming a low coefficient-of-thermal-expansion (CTE) layer on the first silicon (111) surface of the first silicon substrate, the low CTE layer having a CTE less than a CTE of silicon;
• forming another low CTE layer on the second silicon (111) surface of the first silicon substrate, the another low CTE layer having a CTE less than the CTE of silicon;
• bonding the first silicon substrate to a second silicon substrate in a manner so that the low CTE layer is bonded between the first and second silicon substrates, the second silicon substrate having a silicon (100) surface interfacing with the low CTE layer at a first interface;
• thinning the first silicon substrate from the second side in a manner so that the thinned first silicon substrate is substantially thinner than the second silicon substrate;
• forming a buffer layer over the second side of the thinned first silicon substrate, the buffer layer having a CTE greater than the CTE of silicon;
• epi-growing a III-V family layer over the buffer layer, the III-V family layer having a CTE greater than the CTE of the buffer layer;
• and
• after the epi-growing, cooling the III-V family layer, the buffer layer, the low CTE layer, and the first and second silicon substrates to about a room temperature, wherein the cooling causes the III-V family layer and the buffer layer to contract more than the low CTE layer which creates a tensile stress at a second interface between the low CTE layer and the III-V family layer and the buffer layer, wherein the cooling causes the second silicon substrate having the silicon (100) surface to contract more than the low CTE layer which creates a compressive stress at the first interface between the silicon (100) surface of the second silicon substrate and the low CTE layer, and wherein the tensile stress at the second interface and the compressive stress at the first interface substantially balance each other out during the cooling such that the semiconductor device remains substantially flat after the cooling.

A semiconductor device, comprising:

• a substrate having a first coefficient-of-thermal-expansion (CTE), the substrate having a silicon (100) surface;
• a first layer having a second CTE disposed directly on the silicon (100) surface of the substrate such that the first layer interfaces with the silicon (100) surface at a first interface;
• a thin substrate over the first layer, the thin substrate having a third CTE that is greater than the first CTE, the thin substrate having a silicon (111) surface interfacing with the first layer at a second interface;
• and
• a second layer having a fourth CTE disposed over the thin substrate, wherein the fourth CTE is greater than the second CTE,
• wherein a tensile stress at the second interface caused by the second layer is balanced out by a compressive stress at the first interface caused by the silicon (100) surface of the substrate such that the semiconductor device remains substantially flat.