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AssigneeSTMicroelectonics S.r.l.
InventorsPietro Montanini, Marta Mottura, Giuseppe Croce
Estimating the term…
An embodiment of an integrated circuit includes first and second semiconductor layers and a contact region disposed in the second layer. The first semiconductor layer is of a first conductivity, and the second semiconductor layer is disposed over the first layer and has a surface. The contact region is contiguous with the surface, contacts the first layer, includes a first inner conductive portion, and includes an outer conductive portion of the first conductivity. The contact region may extend deeper than conventional contact regions, because where the inner conductive portion is formed from a trench, doping the outer conductive portion via the trench may allow one to implant the dopants more deeply than conventional techniques allow.
A method for manufacturing an integrated electronic device, comprising:
A method for manufacturing an integrated electronic device, comprising:
A method for manufacturing an integrated electronic device, comprising:
A method for manufacturing an integrated electronic device, comprising:
A method for manufacturing an integrated circuit, comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies: semiconductor regions…
Of igfets: contact regions to the substrate regions
Electrodes characterised by their shapes, relative sizes or dispositions: electrodes not carrying the current to be rectified, amplified,…
Manufacture or treatment: of interconnections within wafers or substrates
About 2 years 2 months of term left · ends 15 Dec 2028 (estimated)
The present application is related to U.S. patent application Ser. No. 12/335,178 entitled DEEP GUARD REGIONS FOR REDUCING LATCH-UP IN ELECTRONICS DEVICES filed Dec. 15, 2008, and which is incorporated herein by reference in its entirety.
An embodiment of the present invention relates to the electronics field. Particularly, an embodiment of the present invention relates to contact elements of integrated electronic devices; more particularly, these elements are used to contact covered layers of the electronic devices (such as substrates or buried layers).
Electronic devices are generally integrated in a composite chip of semiconductor material; the chip includes a substrate defining a mechanical support for an active layer (typically including one or more epitaxial layers), which active layer houses different electronic components of the device (such as MOSFET transistors); sometimes, one or more (highly doped) buried layers are also enclosed between the substrate and the active layer, or within the active layer (between a pair of adjacent epitaxial layers).
Features and the advantages of one or more embodiments will be best understood by reference to the following detailed description, given purely by way of a non-restrictive indication, to be read in conjunction with the accompanying drawings. In this respect, it is expressly intended that the figures are not necessary drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein. Particularly:
FIG. 1 shows a cross-section view of a schematic structure of an electronic device according to an embodiment of the present invention;
FIGS. 2A through 2G are cross-section views illustrating the main phases of the manufacturing process of an integrated electronic device, according to an embodiment of the present invention;
With reference now to the figures, FIG. 1 shows a cross-section view of an electronic device 100. As usual, the concentrations of N-type and P-type doping impurities are denoted by adding the sign + or the sign − to the letters N and P to indicate a high or low concentration of impurities, respectively, or the sign ++ or the sign −− to indicate a very high or a very low concentration of impurities, respectively; the letters N and P without the addition of any sign + or − denote concentrations of intermediate value.
In particular, the device 100 (for example, of the smart power type) is formed in a chip including a semiconductor substrate 105 (for example, of the P+ type of conductivity). The electronic components of the device 100—either of the power type or of the logic type (not shown in the figure)—are integrated in a semiconductor active layer 110 (for example, of the P− type), which is stacked on the substrate 105.
The device 100 includes a deep contact 112 extending through the active layer 110 down to the substrate 105; this deep contact 112 is used to collect undesired currents that are injected by the electronic components towards the substrate 105 (and towards the active layer 110 as well).