Gate stack for high-K/metal gate last process

A method for fabricating an integrated circuit device, the method comprising:

• providing a substrate;
• forming a high-k dielectric layer over the substrate;
• forming a multi-layer capping layer over the high-k dielectric layer, wherein the multi-layer capping layer includes at least one titanium nitride layer and at least one tantalum nitride layer;
• after forming the multi-layer capping layer, forming a dummy gate over the multi-layer capping layer;
• performing a patterning process to form a gate stack including the dummy gate, multi-layer capping layer, and high-k dielectric layer;
• performing a gate replacement process, wherein the dummy gate in the gate stack is replaced with a metal gate electrode, the metal gate electrode being formed over the multi-layer capping layer.

A method comprising:

• providing a substrate;
• forming a gate dielectric layer over the substrate;
• forming a titanium nitride layer over the gate dielectric layer;
• forming a tantalum nitride layer over the titanium nitride layer;
• after forming the tantalum nitride layer over the titanium nitride layer, forming a dummy gate layer over the tantalum nitride and titanium nitride layers;
• forming a first gate stack in a n-type metal metal-oxide-semiconductor transistor (NMOS) region and a second gate stack in a p-type metal-oxide-semiconductor transistor (PMOS) region;
• removing the dummy gate layer from the first gate stack, resulting in a first opening, wherein the tantalum nitride layer is exposed;
• removing the dummy gate layer from the second gate stack, resulting in a second opening, wherein the tantalum nitride layer is exposed;
• forming a first metal layer in the first opening, the first metal layer having a n-type work function;
• and
• forming a second metal layer in the second opening, the second metal layer having a p-type work function.