Method of fabricating dual trench isolated epitaxial diode array

A method of fabricating dual trench isolated epitaxial diode array, characterized by comprising the following steps:

• (A) form heavily-doped first conductivity type regions on the substrate of the first conductivity type, and then form heavily-doped second conductivity type regions on said heavily-doped first conductivity type regions;
• (B) form an epitaxial layer on heavily-doped second conductivity type regions;
• (C) form first trenches deep to heavily-doped first conductivity type regions by lithography and etch so as to divide heavily-doped second conductivity type regions into multiple word lines;
• then form oxide layer on the inner surface of first trenches by thermal oxidization before polysilicon is filled into first trenches as insulating isolation layer;
• remove the polysilicon on the top of the first trenches by etching back before oxide is filled in, and then form the first trench isolation structures after planarization process;
• (D) form second trenches vertical to the first trench isolation structures over word lines by lithography and etch;
• then form an oxide layer on the inner surface of second trenches before the insulation material is filled into second trenches by chemical vapor deposition, and form the second trench isolation structures after planarization process;
• (E) divide the epitaxial layer into multiple isolation regions by the first and second trench isolation structures, wherein isolation regions of both ends of the same word line serve as the pickup regions of the word line and the remaining isolation regions serve as diode array cell regions;
• form diode P+ type regions and lightly doped N type regions in diode array cell regions by lithography, ion implantation and annealing so as to form diode array cells;
• isolate word lines from each other by first trench isolation structures and isolate diode array cells on the same word line by second trench isolation structures;
• (F) form word line connect by ion implantation in the pickup regions of word lines so as to reduce series resistance of word lines;
• fabricating memory cells over diode array cells and pick up bit lines.