Application of HIPIMS to through silicon via metallization in three-dimensional wafer packaging

A method of fabricating a stacked arrangement of a plurality of semiconductor substrates collectively supporting an integrated circuit, the method comprising:

• forming a trench in a first semiconductor substrate, said trench comprising an opening at a top of the first semiconductor substrate and substantially vertical side walls, said trench comprising an aspect ratio of at least 10:1;
• supporting the first semiconductor substrate including the trench with a pedestal;
• sputtering an electrically-conductive material on interior side walls of the trench according to a method comprising:
• providing a magnetic field adjacent to a surface of a target formed at least in part from the electrically-conductive material to be sputtered onto the interior surfaces of the trench;
• applying a DC voltage between an anode and a cathode in a plurality of pulses, wherein the cathode includes the target;
• applying a pulsed high-frequency signal comprising a plurality of high-frequency pulses to the pedestal supporting the first semiconductor substrate to generate a self-bias field adjacent to said first semiconductor substrate, said high-frequency signal being applied to the pedestal at a frequency within a range of from about 1 MHz to about 70 MHz during the high-frequency pulses and each of the high frequency pulses having a duration that extends beyond termination of the pulse of the DC voltage between the anode and the cathode;
• and
• during each pulse of the voltage applied between the anode and the cathode, depositing the electrically-conductive material from the target onto the substantially vertical side walls of the trench formed in the semiconductor substrate;
• and
• subsequent to sputter depositing the electrically-conductive material onto the interior side walls of the trench, removing a portion of semiconductor material adjacent to a bottom planar surface of the semiconductor substrate to at least partially expose the electrically-conductive material on the side walls at the bottom planar surface of the semiconductor substrate.

A sputtering apparatus for magnetically-enhanced sputtering an electrically-conductive material onto interior surfaces of a trench formed in a semiconductor substrate, said trench comprising substantially vertical side walls and an aspect ratio of at least 10:1, said system comprising:

• a housing defining a substantially enclosed chamber;
• a pedestal exposed to said chamber for supporting the semiconductor substrate at an appropriate position within said chamber during sputtering;
• a magnet assembly for providing a magnetic field adjacent to a surface of a target formed at least in part from the electrically-conductive material to be sputtered onto the interior surfaces of the trench;
• a DC power supply for applying a DC voltage between an anode and a cathode in a plurality of pulses, wherein the cathode includes the target;
• a variable power source electrically connected to the pedestal for applying a pulsed high-frequency signal comprising a plurality of high-frequency pulses to the pedestal for supporting the semiconductor substrate to generate a self-bias field adjacent to said semiconductor substrate;
• and
• a controller for controlling the variable power source to generate the pulsed high-frequency signal at a frequency within a range from about 1 MHz to about 70 MHz during the high-frequency pulses and applying the high-frequency signal to the pedestal such that each of the high-frequency pulses has a duration that extends beyond termination of the pulse of the DC voltage between the anode and the cathode.