# US 8,474,033 B2 · Computer or microchip with a master controller connected by a secure control bus to networked microprocessors or cores > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,474,033 B2 - Document ID: US8474033B2 - Status: Granted - Kind: B2 - Application number: 13/555,750 - Filed: 2012-07-23 - Published: 2012-12-13 - Granted: 2013-06-25 - Earliest claimed: 2010-01-26 - Applicants: Frampton E. Ellis - Inventors: Frampton E. Ellis - Web page: https://patentgrep.com/patent/US8474033B2 ## CPC - H04L 63/02: {for separating internal from external traffic, e.g. firewalls} - G06F 21/50: Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems - G06F 21/85: interconnection devices, e.g. bus-connected or in-line devices - H04L 63/0227: {Filtering policies (mail message filtering H04L51/212)} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A computer or microchip configured to be securely controlled through a secure control bus, including through a private network. The computer or microchip includes a secure private unit protected by an inner hardware-based access barrier or firewall; an unprotected public unit including at least one network connection configured to connect to a network; a separate private network connection located in the secure private unit; a microprocessor, core or processing unit configured for general purposes located in the unprotected public unit and separate from the access barrier or firewall; a secure control bus isolated from input from both the network and components of the unprotected public unit; and a master controlling device in the private unit being configured for securely controlling an operation executed by the microprocessor, core or processing unit via a connection to the secure control bus, including through the separate private network to the separate private network connection. ## Claims ### Claim 1 A computer or microchip configured to be securely controlled through a private network, said computer or microchip comprising: at least a secure private unit of said computer or microchip that is protected by an inner hardware-based access barrier or firewall; an unprotected public unit of said computer or microchip, said unprotected public unit including at least one network connection configured to connect to a network of computers including the Internet; at least a separate private network connection configured for connection to at least said private network of computers, at least said separate private network connection being located in at least said secure private unit of said computer or microchip; at least one microprocessor, core or processing unit configured for general purposes is located in said unprotected public unit, wherein said at least one microprocessor, core or processing unit is separate from said inner hardware-based access barrier or firewall; at least a master controlling device for the computer or microchip located in said secure private unit; and a secure control bus configured to connect at least said master controlling device with at least said microprocessor, core or processing unit located in said unprotected public unit, said secure control bus being isolated from input from said network and input from components of said unprotected public unit; and said master controlling device being configured for securely controlling at least one operation executed by at least one said microprocessor, core or processing unit in said unprotected public unit, said secure control being provided by said master controlling device in said secure private unit through said separate private network to said additional and separate private network connection in said secure private unit and via said secure control bus. ### Claim 2 (depends on 1) The computer or microchip of claim 1, wherein said master controlling device comprises a microprocessor, core or processing unit configured for general purposes. ### Claim 3 (depends on 2) The computer or microchip of claim 2, wherein said master controlling device comprises a non-volatile memory. ### Claim 4 (depends on 2) The computer or microchip of claim 2, wherein said secure control bus provides and ensures direct preemptive control by said master controlling device over said unprotected public unit. ### Claim 5 (depends on 2) The computer or microchip of claim 2, wherein said secure control bus is configured such that it cannot be affected, interfered with, altered, read from or written to, or superseded by any part of said unprotected public unit or by input from said network. ### Claim 6 (depends on 2) The computer or microchip of claim 2, wherein said secure control bus is configured such that it can be used by said master controlling device to control one or more secondary controllers located on said secure control bus. ### Claim 7 (depends on 6) The computer or microchip of claim 6, wherein said one or more secondary controllers are located in the unprotected public unit. ### Claim 8 (depends on 7) The computer or microchip of claim 7, wherein said one or more secondary controllers are used to control one or more of said at least one microprocessor, core or processing unit located in said unprotected public unit. ### Claim 9 (depends on 8) The computer or microchip of claim 8, wherein said one or more secondary controllers are integrated with one or more of said at least one microprocessor, core or processing unit located in said unprotected public unit. ### Claim 10 (depends on 2) The computer or microchip of claim 2, wherein said secure control bus is wired, wireless or a channel. ### Claim 11 (depends on 2) The computer or microchip of claim 2, wherein said secure control bus is configured to provide a connection to control a firewall located on the periphery of said computer or microchip. ### Claim 12 (depends on 2) The computer or microchip of claim 2, wherein a secure control bus is configured to connect at least said master controlling device with at least two of said microprocessors, cores or processing units located in said unprotected public unit. ### Claim 13 (depends on 2) The computer or microchip of claim 2, wherein a secure control bus is configured to connect at least said master controlling device with at least six of said microprocessors, cores or processing units located in said unprotected public unit. ### Claim 14 A computer or microchip configured to be securely controlled, said computer or microchip comprising: an inner hardware-based access barrier or firewall communicatively connected to a secure private unit of said computer or microchip that is protected by said inner hardware-based access barrier or firewall, said inner hardware-based access barrier or firewall being located between said secure private unit and an unprotected public unit of said computer or microchip, and said unprotected public unit being configured to connect to a network of computers including the Internet; at least one microprocessor, core or processing unit located in said unprotected public unit, wherein said at least one microprocessor, core or processing unit is configured for general purposes and is separate from said inner hardware-based access barrier or firewall; at least a master controlling device for the computer or microchip located in said secure private unit; and a secure control bus configured to connect at least said master controlling device with at least said at least one microprocessor, core or processing unit located in said unprotected public unit, and said secure control bus being isolated from input from said network and input from components of said unprotected public unit; and said master controlling device being configured for securely controlling at least one operation executed by at least one said microprocessor, core or processing unit in said unprotected public unit, said secure control being provided by said master controlling device in said secure private unit via said secure control bus. ### Claim 15 (depends on 14) The computer or microchip of claim 14, wherein said master controlling device comprises a microprocessor, core or processing unit configured for general purposes. ### Claim 16 (depends on 15) The computer or microchip of claim 15, wherein said master controlling device comprises a non-volatile memory. ### Claim 17 (depends on 15) The computer or microchip of claim 15, wherein said secure control bus provides and ensures direct preemptive control by said master controlling device over said unprotected public unit. ### Claim 18 (depends on 15) The computer or microchip of claim 15, wherein said secure control bus is configured such that it cannot be affected, interfered with, altered, read from or written to, or superseded by any part of said unprotected public unit or by input from said network. ### Claim 19 (depends on 15) The computer or microchip of claim 15, wherein said secure control bus is configured such that it can be used by said master controlling device to control one or more secondary controllers located on said secure control bus. ### Claim 20 (depends on 19) The computer or microchip of claim 19, wherein said one or more secondary controllers are located in the unprotected public unit. ### Claim 21 (depends on 20) The computer or microchip of claim 20, wherein said one or more secondary controllers are used to control one or more of said at least one microprocessor, core or processing unit located in said unprotected public unit. ### Claim 22 (depends on 21) The computer or microchip of claim 21, wherein said one or more secondary controllers are integrated with one or more of said at least one microprocessor, core or processing unit located in said unprotected public unit. ### Claim 23 (depends on 15) The computer or microchip of claim 15, wherein said secure control bus is wired, wireless or a channel. ### Claim 24 (depends on 15) The computer or microchip of claim 15, wherein said secure control bus is configured to provide a connection to control a firewall located on the periphery of said computer or microchip. ### Claim 25 (depends on 15) The computer or microchip of claim 15, wherein a secure control bus configured to connect at least said master controlling device with at least two of said microprocessors, cores or processing units located in said unprotected public unit. ### Claim 26 (depends on 15) The computer or microchip of claim 15, wherein a secure control bus configured to connect at least said master controlling device with at least six of said microprocessors, cores or processing units located in said unprotected public unit. ### Claim 27 A computer or microchip configured to be securely controlled, said computer or microchip comprising: at least a first secure private unit of said computer or microchip that is protected by at least a first inner hardware-based access barrier or firewall; an unprotected public unit of said computer or microchip, said unprotected public unit being configured to connect to a network of computers including the Internet; at least a second secure private unit that is protected by at least a second hardware-based access barrier or firewall, said second secure private unit including at least one computer or microchip component; at least one microprocessor, core or processing unit configured for general purposes is located in said unprotected public unit, wherein said at least one microprocessor, core or processing unit is separate from said inner hardware-based access barrier or firewall; at least a master controlling device for the computer or microchip located in at least said first secure private unit; and a secure control bus configured to connect at least said master controlling device with at least said microprocessor, core or processing unit located in said unprotected public unit and said at least one component in said second secure private unit, and said secure control bus being isolated from input from said network and input from components of said unprotected public unit; and said master controlling device being configured for securely controlling at least one operation executed by at least one said microprocessor, core or processing unit in said unprotected public unit and said at least one component in said second secure private unit, said secure control being provided by said master controlling device in said first secure private unit via said secure control bus. ### Claim 28 (depends on 27) The computer or microchip of claim 27, wherein said master controlling device comprises a microprocessor, core or processing unit configured for general purposes. ### Claim 29 (depends on 28) The computer or microchip of claim 28, wherein said master controlling device comprises a non-volatile memory. ### Claim 30 (depends on 28) The computer or microchip of claim 28, wherein said secure control bus provides and ensures direct preemptive control by said master controlling device over said unprotected public unit. ### Claim 31 (depends on 28) The computer or microchip of claim 28, wherein said secure control bus is configured such that it cannot be affected, interfered with, altered, read from or written to, or superseded by any part of said unprotected public unit or by input from said network. ### Claim 32 (depends on 28) The computer or microchip of claim 28, wherein said secure control bus is configured such that it can be used by said master controlling device to control one or more secondary controllers located on said secure control bus. ### Claim 33 (depends on 32) The computer or microchip of claim 32, wherein said one or more secondary controllers are located in the unprotected public unit. ### Claim 34 (depends on 33) The computer or microchip of claim 33, wherein said one or more secondary controllers are used to control one or more of said at least one microprocessor, core or processing unit located in said unprotected public unit. ### Claim 35 (depends on 34) The computer or microchip of claim 34, wherein said one or more secondary controllers are integrated with one or more of said at least one microprocessor, core or processing unit located in said unprotected public unit. ### Claim 36 (depends on 28) The computer or microchip of claim 28, wherein said secure control bus is wired, wireless or a channel. ### Claim 37 (depends on 28) The computer or microchip of claim 28, wherein said secure control bus is configured to provide a connection to control a firewall located on the periphery of said computer or microchip. ### Claim 38 (depends on 28) The computer or microchip of claim 28, wherein a secure control bus configured to connect at least said master controlling device with at least two of said microprocessors, cores or processing units located in said unprotected public unit. ### Claim 39 (depends on 28) The computer or microchip of claim 28, wherein a secure control bus configured to connect at least said master controlling device with at least six of said microprocessors, cores or processing units located in said unprotected public unit. ### Claim 40 A computer or microchip configured to be securely controlled, said computer or microchip comprising: at least one microprocessor, core or processing unit being configured for general purposes and configured to connect to a network of computers including the Internet; at least a master controlling device for the computer or microchip; and a secure control bus configured to connect at least said master controlling device with at least said at least one microprocessor, core or processing unit, and said secure control bus being isolated from input from said network and input from components of said computer or microchip other than said master controlling device; and said master controlling device being configured for securely controlling at least one operation executed by at least one said microprocessor, core or processing unit, said secure control being provided by said master controlling device via said secure control bus. ### Claim 41 (depends on 40) The computer or microchip of claim 40, wherein said master controlling device comprises a microprocessor, core or processing unit configured for general purposes. ### Claim 42 (depends on 41) The computer or microchip of claim 41, wherein said master controlling device comprises a non-volatile memory. ### Claim 43 (depends on 41) The computer or microchip of claim 41, wherein said secure control bus is configured such that it can be used by said master controlling device to control one or more secondary controllers located on said secure control bus. ### Claim 44 (depends on 41) The computer or microchip of claim 41, wherein said secure control bus is wired, wireless or a channel. ### Claim 45 A computer or microchip configured to be securely controlled through a private network, said computer or microchip comprising: at least one network connection to a network of computers including the Internet; at least a separate private network connection configured for connection to at least a private network of computers, at least said separate private network connection being located in a hardware protected area of said computer or microchip, at least one microprocessor, core or processing unit configured for general purposes and configured to connect to said at least one connection to a network of computers including the Internet; at least a master controlling device for the computer or microchip located in said hardware protected area; and a secure control bus configured to connect at least said master controlling device with at least said microprocessor, core or processing unit, said secure control bus being isolated from input from said network and input from components of said computer or microchip other than said master controlling device; and said master controlling device being configured for securely controlling at least one operation executed by at least one said microprocessor, core or processing unit, said secure control being provided by said master controlling device through said separate private network to said additional and separate private network connection in said hardware protected area and through said secure control bus. ### Claim 46 (depends on 45) The computer or microchip of claim 45, wherein said master controlling device comprises a microprocessor, core or processing unit configured for general purposes. ### Claim 47 (depends on 46) The computer or microchip of claim 46, wherein said master controlling device comprises a non-volatile memory. ### Claim 48 (depends on 46) The computer or microchip of claim 46, wherein said secure control bus is configured such that it can be used by said master controlling device to control one or more secondary controllers located on said secure control bus. ### Claim 49 (depends on 46) The computer or microchip of claim 46, wherein said secure control bus is wired, wireless or a channel.