Reliable communications in on-chip networks
AssigneeEmpire Technology Development LLC
InventorsWilliam H. Mangione-Smith, Onur Mutlu
Life of this patent
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Abstract
Techniques for reliable communication in an on-chip network of a multi-core processor are provided. Packets are tagged with tags that define reliability requirements for the packets. The packets are routed in accordance with the reliability requirements. The reliability requirements and routing using them can ensure reliable communication in the on-chip network.
Claims25
In a multi-core processor having a switch fabric providing communication among a plurality of cores, a method for delivering a packet in the switch fabric, the method comprising:
- originating the packet at an originating core included in the plurality of cores, the core including a processor and a network switch, wherein the plurality of cores are the nodes in the switch fabric;
- tagging the packet with a tag included as part of the packet, wherein the tag defines a reliability requirement for the packet, wherein the reliability requirement controls delivery of the packet in the switch fabric;
- and
- delivering the packet to a destination core in compliance with the reliability requirement, wherein the reliability requirement enables the switch fabric to dynamically adjust performance of the switch fabric in the delivery of the packet.
A method for routing a packet in a switch fabric, the method comprising:
- receiving a packet at a core of a multi-core processor from an originating core, the core including at least a processor and a network switch for routing packets and the packet including a tag as part of the packet;
- examining a reliability requirement defined by the tag, wherein the reliability requirement identifies delivery options for the packet in the switch fabric;
- and
- transmitting the packet in the switch fabric to a destination core while complying with the reliability requirement defined by the tag, wherein the core, the originating core and the destination core are part of the nodes in the switch fabric.
A multi-core processor having a switch fabric for routing a packet, the processor comprising:
- a plurality of connections;
- a plurality of cores connected by the plurality of connections to form the switch fabric, the plurality of cores including an originating core and a destination core, each core including a processor and a network switch, wherein the originating core generates the packet and tags the packet with a tag included as part of the packet, wherein the tag defines a reliability requirement, wherein the packet is delivered to the destination core via the switch fabric according to the reliability requirement, wherein the plurality of cores are the nodes in the switch fabric.
Dependencies are inferred from the claim text.