M-bit race delay adder and method of operation

A data processor, comprising:

• an instruction execution pipeline comprising N processing stages, each of said N processing stages capable of performing one of a plurality of execution steps associated with a pending instruction being executed by said instruction execution pipeline, wherein at least one of said N processing stages comprises an M-bit adder capable of n M-bit adder capable of receiving a first M-bit argument, a second M-bit argument, and a carry-in (CI) bit, the M-bit adder comprising:
• M adder cells arranged in R rows including a first row and R−1 subsequent rows, each row subsequent to the first row having more adder cells than a preceding row,
• wherein each row of adder cells includes a least significant adder cell and at least one subsequent adder cell,
• wherein each adder cell is configured to receive
• a data bit, AX, from the first M-bit argument, and
• a data bit, BX, from the second M-bit argument,
• wherein each adder cell subsequent to the least significant adder cell within each row subsequent to the first row is configured to receive
• a first conditional carry-in bit, CX−1(1), from a preceding adder cell within the row, and
• a second conditional carry-in bit, CX−1(0), from the preceding adder cell within the row, and
• wherein each adder cell within a row subsequent to the first row is configured to generates a first conditional carry-out bit CX(1), and a second conditional carry-out bit, CX(0), wherein the CX(1) bit is calculated assuming a carry-out bit from a most significant adder cell within the preceding row is a 1 and the CX(0) bit is calculated assuming the carry-out bit from the most significant adder cell within the preceding row is a 0,
• wherein each adder cell subsequent to the least significant adder cell within each row further comprises:
• first and second passgates receiving the first and second conditional carry-in bits CX−1(1) and CX−1(0), respectively;
• and
• first and second inverters coupled to the first and second passgates,
• wherein the respective adder cell is configured to generate the first conditional carry-out bit CX(1) and the second conditional carry-out bit CX(0) by inverting and propagating the first conditional carry-in bit CX−1(1) and the second conditional carry-in bit CX−1(0), respectively, and
• wherein alternate adder cells subsequent to the least significant adder cell within each row are configured to invert and propagate the first and second conditional carry-in bits CX−1(1) and CX−1(0) as the first and second conditional carry-out bits CX(1) and CX(0) when the data bit AX and the data bit BX are equal, and
• wherein intervening adder cells subsequent to the least significant adder cell within each row are configured to invert and propagate the first and second conditional carry-in bits CX−1(1) and CX−1(0) as the first and second conditional carry-out bits CX(1) and CX(0) when the data bit AX and the data bit BX are not equal.