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AssigneeBridge Crossing, LLC
InventorsMario D. Nemirovsky, Adolfo M. Nemirovsky, Narendra Sankar
Estimating the term…
A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler logic. The logic detects and maps interrupts and exceptions to one or more specific streams. In some embodiments, one interrupt or exception may be mapped to two or more streams, and in others two or more interrupts or exceptions may be mapped to one stream. Mapping may be static and determined at processor design, programmable, with data stored and amendable, or conditional and dynamic, the interrupt logic executing an algorithm sensitive to variables to determine the mapping. Interrupts may be external interrupts generated by devices external to the processor software (internal) interrupts generated by active streams, or conditional, based on variables. After interrupts are acknowledged, streams to which interrupts or exceptions are mapped are vectored to appropriate service routines.
A processor system having an interstream control arrangement, comprising:
A processor dynamically configurable to define and enable an supervisory thread and a subservient thread, comprising:
Dependencies are inferred from the claim text.