# US 8,465,908 B2 · Method for forming fine patterns of semiconductor device

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- Number: US 8,465,908 B2
- Document ID: US8465908B2
- Status: Granted
- Kind: B2
- Application number: 12/272,192
- Filed: 2008-11-17
- Published: 2009-12-24
- Granted: 2013-06-18
- Earliest claimed: 2008-11-17
- Assignees: Hynix Semiconductor Inc.
- Applicants: Jae Seung Choi
- Inventors: Jae Seung Choi
- Web page: https://patentgrep.com/patent/US8465908B2

## CPC

- G03F 7/0035: {Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface}
- G03F 7/095: having more than one photosensitive layer (G03F7/075 takes precedence)
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10P 50/73: {using masks for insulating materials}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10P 76/4088: {Processes for improving the resolution of the masks}
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming fine patterns of a semiconductor device employs a double patterning characteristic using a mask for forming a first pattern including a line pattern and a mask for separating the line pattern, and a reflow characteristic of a photoresist pattern.

## Claims

### Claim 1

A method for forming fine patterns of a semiconductor device, the method comprising:
forming a first pattern having a line type over an underlying layer in a cell region;
forming first spacers on the sidewalls of the first pattern in the cell region and forming a spacer insulating film over the underlying layer in the peripheral circuit region;
forming a gap-fill insulating film between the first spacers in the cell region and over the spacer insulating film in the peripheral circuit region;
removing the first spacers to form a second pattern between the first pattern;
forming a first photoresist pattern that defines a contact hole in the cell region and defines an active region in a peripheral circuit region;
etching the first pattern and the second pattern of the cell region, and the spacer insulating film and the gap-fill insulating film of the peripheral circuit region using the first photoresist pattern as a mask to divide each of the first pattern and the second pattern in the cell region and form island pattern in the peripheral circuit region; and
etching the underlying layer using the divided first pattern, the divided second pattern and the island pattern.

### Claim 2 (depends on 1)

The method according to claim 1, comprising forming the first pattern by:
forming a hard mask layer over the underlying layer;
forming a second photoresist pattern over the hard mask layer using a first exposure mask having a line-type shading region; and
etching the hard mask layer using the second photoresist pattern as a mask to pattern the hard mask layer.

### Claim 3 (depends on 2)

The method according to claim 2, wherein the spacer insulating film comprises a material having a higher etching selectivity than those of the hard mask layer and the gap-fill insulating film.

### Claim 4 (depends on 2)

The method according to claim 2, wherein the gap-fill insulating film comprises a material having a lower etching selectivity than that of the hard mask layer.

### Claim 5 (depends on 1)

The method according to claim 1, comprising forming the first photoresist pattern by:
forming a photoresist film over the first pattern and the second pattern and the underlying layer; and
patterning the photoresist pattern using a second exposure mask having a transmitting region that defines the contact hole in the cell region and having a shading region that defines the island pattern in the peripheral circuit region.

### Claim 6 (depends on 1)

The method according to claim 1, further comprising;
reducing a critical dimension (CD) of the contact hole before etching the first pattern and the second pattern.

### Claim 7 (depends on 6)

The method according to claim 6, comprising reducing the critical dimension (CD) of the contact hole by a method selected from the group consisting of reflowing the first photoresist pattern, forming a resolution enhancement lithography assisted by chemical shrink (RELACS) material in the first photoresist pattern, and forming a second spacer on the sidewall of the first photoresist pattern.

### Claim 8 (depends on 1)

The method according to claim 1, comprising forming the first spacers on the sidewalls of the first pattern by forming the spacer insulating film on the sidewalls of the first pattern.

### Claim 9 (depends on 8)

The method according to claim 8, comprising forming the gap-fill insulating film between the first spacers by:
forming a gap-fill insulating material to fill a space between the first spacers; and
planarizing the gap-fill insulating material until the spacer insulating film is exposed.

### Claim 10 (depends on 9)

The method according to claim 9, comprising planarizing the gap-fill insulating material by an etch-back or a chemical mechanical polishing process.

### Claim 11 (depends on 1)

The method according to claim 1, comprising removing the first spacers by using the gap-fill insulating film as an etching mask and using the first pattern and the underlying layer as an etching barrier.