# US 8,465,657 B2 · Post chemical mechanical polishing etch for improved time dependent dielectric breakdown reliability > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,465,657 B2 - Document ID: US8465657B2 - Status: Granted - Kind: B2 - Application number: 11/833,283 - Filed: 2007-08-03 - Published: 2007-11-22 - Granted: 2013-06-18 - Earliest claimed: 2005-05-10 - Assignees: International Business Machines Corporation - Applicants: Kaushik Chanda; James J. Demarest; Ronald G. Filippi; Roy C. Iggulden; Edward W. Kiewara; Ping-Chuan Wang; Yun-Yu Wang - Inventors: Kaushik Chanda; James J. Demarest; Ronald G. Filippi; Roy C. Iggulden; Edward W. Kiewara; Ping-Chuan Wang; Yun-Yu Wang - Web page: https://patentgrep.com/patent/US8465657B2 ## CPC - B24B 37/042: {operating processes therefor} - H10P 50/73: {using masks for insulating materials} - H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal} - H10W 20/039: {also covering sidewalls of the conductive structures} - H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation} - H10W 20/063: {by forming conductive members before forming protective insulating material} - H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)} - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - Y10T 29/49156: with selective destruction of conductive paths - Y10T 29/49165: by forming conductive walled aperture in base - Y10T 29/49204: Contact or terminal manufacturing - B24B: MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING (grinding of gear teeth B23F, of screw-threads B23G1/36; by electro-erosion B23H; abrasive or related blasting B24C; tools for grinding, buffing or sharpening B24D; polishing compositions C09G1/00; abrasives C09K3/14; electrolytic etching or polishing C25F3/00; grinding arrangements for use on assembled railway tracks E01B31/17); DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ## Abstract Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line. ## Claims ### Claim 1 A method of simultaneously forming different structures in an integrated circuit structure, said method comprising: forming a release layer on a dielectric layer, having a top surface; etching an opening extending through said release layer and into said dielectric layer such that, within said dielectric layer, said opening has a deep first portion and a shallow second portion above and wider than said deep first portion and further such that edges of said release layer at said opening extend laterally over said shallow second portion, said etching comprising isotropically etching said dielectric layer to form said shallow second portion; lining said opening with a liner; filling said opening with a conductor, said lining and said filling resulting in a conductive interconnect line in said shallow second portion and a conductive via in said deep first portion, said conductive interconnect line having lined corners adjacent said top surface of said dielectric layer; polishing said liner and said conductor off of said release layer; and removing said release layer using a process other than chemical mechanical processing such that any trace amounts of said liner and said conductor that remain on said release layer after said polishing are completely removed as said release layer is removed. ### Claim 2 (depends on 1) The method of claim 1, further comprising: after said polishing of said liner and said conductor off of said release layer and before said removing of said release layer, recessing said conductive interconnect line level with said top surface of said dielectric layer; and after said removing of said release layer, depositing a capping layer over said dielectric layer and said conductor. ### Claim 3 (depends on 1) The method of claim 1, said removing of said release layer resulting in a narrow top portion of said conductive interconnect line that extends above said dielectric layer, and said method further comprising: depositing a second dielectric layer over said dielectric layer and said conductive interconnect line such that said second dielectric layer laterally surrounds said narrow top portion of said conductive interconnect line; polishing said second dielectric layer to expose said narrow top portion of said conductive interconnect line; and depositing a capping layer over said second dielectric layer and said narrow top portion of said conductive interconnect line. ### Claim 4 (depends on 1) The method of claim 1, said forming of said release layer comprising depositing an organic material, and said removing of said release layer comprising dissolving said release layer in an organic solvent. ### Claim 5 (depends on 1) The method of claim 1, said forming of said release layer comprising depositing a dielectric material, and said removing of said release layer comprising performing a wet etching process. ### Claim 6 (depends on 1) The method of claim 1, said forming of said release layer comprising depositing one of a metal and a metal nitride, and said removing of said release layer comprising performing a wet etching process. ### Claim 7 (depends on 1) The method of claim 1, said removing of said release layer comprising selectively removing said release layer to prevent etch back of at least one of said dielectric layer and said conductive interconnect line. ### Claim 8 (depends on 1) The method of claim 1, further comprising, after said removing of said release layer, polishing said dielectric layer and said conductive interconnect line level to adjust for any etch back of said dielectric layer and said conductive interconnect line. ### Claim 9 A method of simultaneously forming different structures in an integrated circuit structure, said method comprising: forming a release layer on a dielectric layer, having a top surface, by depositing an organic material; etching an opening extending through said release layer and into said dielectric layer such that, within said dielectric layer, said opening has a deep first portion and a shallow second portion above and wider than said deep first portion and further such that edges of said release layer at said opening extend laterally over said shallow second portion, said etching comprising isotropically etching said dielectric layer to form said shallow second portion; lining said opening with a liner; filling said opening with a conductor, said lining and said filling resulting in a conductive interconnect line in said shallow second portion and a conductive via in said deep first portion, said conductive interconnect line having lined corners adjacent said top surface of said dielectric layer; polishing said liner and said conductor off of said release layer; and removing said release layer by dissolving said release layer in an organic solvent such that any trace amounts of said liner and said conductor that remain on said release layer after said polishing are completely removed as said release layer is removed. ### Claim 10 (depends on 9) The method of claim 9, further comprising: after said polishing of said liner and said conductor off of said release layer and before said removing of said release layer, recessing said conductive interconnect line level with said top surface of said dielectric layer; and after said removing of said release layer, depositing a capping layer over said dielectric layer and said conductor. ### Claim 11 (depends on 9) The method of claim 9, said removing of said release layer resulting in a narrow top portion of said conductive interconnect line that extends above said dielectric layer, and said method further comprising: depositing a second dielectric layer over said dielectric layer and said conductive interconnect line such that said second dielectric layer laterally surrounds said narrow top portion of said conductive interconnect line forming reinforced corners; polishing said second dielectric layer to expose said narrow top portion of said conductive interconnect line; and depositing a capping layer over said second dielectric layer and said narrow top portion of said conductive interconnect line. ### Claim 12 (depends on 9) The method of claim 9, said removing of said release layer comprising selectively removing said release layer to prevent etch back of at least one of said dielectric layer and said conductive interconnect line. ### Claim 13 (depends on 9) The method of claim 9, further comprising, after said removing of said release layer, polishing said dielectric layer and said conductive interconnect line level to adjust for any etch back of said dielectric layer and said conductive interconnect line. ### Claim 14 A method of simultaneously forming different structures in an integrated circuit structure, said method comprising: forming a release layer on a dielectric layer, having a top surface, by depositing a dielectric material; etching an opening extending through said release layer and into said dielectric layer such that, within said dielectric layer, said opening has a deep first portion and a shallow second portion above and wider than said deep first portion and further such that edges of said release layer at said opening extend laterally over said shallow second portion, said etching comprising isotropically etching said dielectric layer to form said shallow second portion; lining said opening with a liner; filling said opening with a conductor, said lining and said filling resulting in a conductive interconnect line in said shallow second portion and a conductive via in said deep first portion, said conductive interconnect line having lined corners adjacent said top surface of said dielectric layer; polishing said liner and said conductor off of said release layer; and removing said release layer by performing a wet etch process such that any trace amounts of said liner and said conductor that remain on said release layer after said polishing are completely removed as said release layer is removed. ### Claim 15 (depends on 14) The method of claim 14, further comprising: after said polishing of said liner and said conductor off of said release layer and before said removing of said release layer, recessing said conductive interconnect line level with said top surface of said dielectric layer; and after said removing of said release layer, depositing a capping layer over said dielectric layer and said conductor. ### Claim 16 (depends on 14) The method of claim 14, said removing of said release layer resulting in a narrow top portion of said conductive interconnect line that extends above said dielectric layer and said method further comprising: depositing a second dielectric layer over said dielectric layer and said conductive interconnect line such that said second dielectric layer laterally surrounds said narrow top portion of said conductive interconnect line forming reinforced corners; polishing said second dielectric layer to expose said narrow top portion of said conductive interconnect line; and depositing a capping layer over said second dielectric layer and said narrow top portion of said conductive interconnect line. ### Claim 17 (depends on 14) The method of claim 14, said removing of said release layer comprising selectively removing said release layer to prevent etch back of at least one of said dielectric layer and said conductive interconnect line. ### Claim 18 (depends on 14) The method of claim 14, further comprising, after said removing of said release layer, polishing said dielectric layer and said conductive interconnect line level to adjust for any etch back of said dielectric layer and said conductive interconnect line. ### Claim 19 A method of simultaneously forming different structures in an integrated circuit structure, said method comprising: forming a release layer on a dielectric layer, having a top surface, by depositing one of a metal and a metal nitride material; etching an opening extending through said release layer and into said dielectric layer such that, within said dielectric layer, said opening has a deep first portion and a shallow second portion above and wider than said deep first portion and further such that edges of said release layer at said opening extend laterally over said shallow second portion, said etching comprising isotropically etching said dielectric layer to form said shallow second portion; lining said opening with a liner; filling said opening with a conductor, said lining and said filling resulting in a conductive interconnect line in said shallow second portion and a conductive via in said deep first portion, said conductive interconnect line having lined corners adjacent said top surface of said dielectric layer; polishing said liner and said conductor off of said release layer; and removing said release layer by performing a wet etch process that selectively removes said release layer such that etch back of at least one of said dielectric layer and said conductive interconnect line is prevented and such that any trace amounts of said liner and said conductor that remain on said release layer after said polishing are completely removed. ### Claim 20 (depends on 19) The method of claim 19, further comprising: after said polishing of said liner and said conductor off of said release layer and before said removing of said release layer, recessing said conductive interconnect line level with said top surface of said dielectric layer; and after said removing of said release layer, depositing a capping layer over said dielectric layer and said conductor. ### Claim 21 (depends on 19) The method of claim 19, said removing of said release layer resulting in a narrow top portion of said conductive interconnect line that extends above said dielectric layer and said method further comprising: depositing a second dielectric layer over said dielectric layer and said conductive interconnect line such that said second dielectric layer laterally surrounds said narrow top portion of said conductive interconnect line forming reinforced corners; polishing said second dielectric layer to expose said narrow top portion of said conductive interconnect line; and depositing a capping layer over said second dielectric layer and said narrow top portion of said conductive interconnect line.