# US 8,464,423 B2 · Method of manufacturing a printed circuit board having metal bumps

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- Number: US 8,464,423 B2
- Document ID: US8464423B2
- Status: Granted
- Kind: B2
- Application number: 13/373,387
- Filed: 2011-11-14
- Published: 2012-03-15
- Granted: 2013-06-18
- Earliest claimed: 2008-11-28
- Assignees: Samsung Electro-Mechanics Co., Ltd.
- Applicants: Myung Sam Kang; Jeong Woo Park; Ok Tae Kim; Kil Yong Yun
- Inventors: Myung Sam Kang; Jeong Woo Park; Ok Tae Kim; Kil Yong Yun
- Web page: https://patentgrep.com/patent/US8464423B2

## CPC

- H05K 1/111: {Pads for surface mounting, e.g. lay-out}
- H05K 1/09: Use of materials for the {conductive, e.g. } metallic pattern
- H05K 1/115: {Via connections; Lands around holes or via connections (H05K1/112 takes precedence)}
- H05K 3/205: {using a pattern electroplated or electroformed on a metallic carrier}
- H05K 3/4007: {Surface contacts, e.g. bumps (H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3465)}
- H05K 3/28: Applying non-metallic protective coatings {(H05K3/0091 takes precedence; methods for intermediate insulating layers for build-up multilayer circuits H05K3/4673)}
- H05K 2201/0367: Metallic bump or raised conductor not used as solder bump
- H05K 2203/0323: Working metal substrate or core, e.g. by etching, deforming
- H05K 2203/0376: Etching temporary metallic carrier substrate
- Y02P 70/50: Manufacturing or production processes characterised by the final manufactured product
- Y10T 29/49124: On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T 29/49147: Assembling terminal to base
- Y10T 29/49155: Manufacturing circuit on or in base
- Y10T 29/49204: Contact or terminal manufacturing
- Y10T 29/49222: forming array of contacts or terminals
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

A method of manufacturing a printed circuit board having a metal bump, including: forming a recess for creation of the metal bump on a first carrier, forming a first barrier layer on the first carrier, and forming an upper circuit layer on the first barrier layer, the upper circuit layer including a metal bump charged in the recess and a circuit pattern; forming a second barrier layer on a second carrier, and forming a lower circuit layer on the second barrier layer; preparing an insulating layer, and transferring the upper and lower circuit layers to the insulating layer; removing the first and second carriers; and removing the first and second barrier layers.

## Claims

### Claim 1

A method of manufacturing a printed circuit board having a metal bump, comprising:
forming a recess for creation of the metal bump on a first carrier, forming a first barrier layer on the first carrier, and forming an upper circuit layer on the first barrier layer, the upper circuit layer including a metal bump charged in the recess and a circuit pattern;
forming a second barrier layer on a second carrier, and forming a lower circuit layer on the second barrier layer;
preparing an insulating layer, and transferring the upper and lower circuit layers to the insulating layer;
removing the first and second carriers; and
removing the first and second barrier layers.

### Claim 2 (depends on 1)

The method according to claim 1, further comprising, after removing the first and second barrier layers, forming solder resist layers on both sides of the insulating layer.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the first and second carriers and the upper and lower circuit layers are made of electroconductive metal, and the first and second barrier layers are made of a metal that is selectively etched with respect to metals from which the first and second carriers and the upper and lower circuit layers are made.

### Claim 4 (depends on 1)

The method according to claim 1, further comprising, after removing the first and second carriers, forming a via for electrical connection between the upper and lower circuit layers.