High speed syndrome-based FEC encoder and system using same

A communication system, comprising:

• a decoder system comprising:
• a plurality of N-parallel syndrome generators, each of the N-parallel syndrome generators coupled to a parallel input data stream and being adapted to perform a calculation each cycle with N symbols from the input parallel data stream;
• a plurality of key equation determination devices, each key equation determination device coupled to at least one of the N-parallel syndrome generators and being adapted to determine at least one error polynomial;
• a plurality of N-parallel error determination and correcting devices, one for each of the N-parallel syndrome generators, each N-parallel error correction and determination device coupled to one of the key equation determination devices and being adapted to use the at least one error polynomial produced by the one key equation determination device to correct errors in the parallel input data stream;
• and
• an encoder system coupled to the decoder system and comprising:
• a plurality of N-parallel encoders, each of the N-parallel encoders adapted to accept N symbol inputs, in parallel, during a cycle and produce, in parallel, N symbol outputs during a cycle, and wherein each N-parallel encoder is adapted to produce a plurality of redundancy symbols after a predetermined number of input symbols have been input to the encoder, wherein said N symbol inputs comprise a plurality of input bits, wherein said plurality of redundancy symbols comprise a plurality of output bits, wherein each N-parallel encoder comprises an input delay unit and an output delay unit, wherein each input delay unit delays only a subset of said plurality of input bits, and wherein each output delay unit delays only a subset of said plurality of output bits;
• and
• a device coupled to the N-parallel encoders and adapted to create an M-parallel frame, the M-parallel frame adapted to hold a plurality of codewords, each codeword comprising a plurality of symbols.