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US 8,446,173 B1Granted
Scalable high-swing transmitter with rise and/or fall time mismatch compensation
AssigneePMC-Sierra, Inc.
InventorsJulien Faucher, Michael Ben Venditti
Life of this patent
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Abstract
Disclosed is a high-swing voltage-mode transmitter or line driver. The transmitter can operate over a wide range of supply voltages. Increasing the available output swing merely involves increasing the supply voltage; the circuit adapts to maintain the desired output impedance. This allows for a tradeoff between output amplitude and power consumption. Another advantage of the proposed architecture is that it compensates for process, voltage, and temperature (PVT) and mismatch variations so as to keep rise and fall times matched. This feature reduces common-mode noise and hence EMI in systems in which the transmitter is used.
Claims37
An apparatus comprising:
- an output driver configured to generate a differential output signal, wherein the output driver comprises a first subcircuit and a second subcircuit,
- wherein the first subcircuit is configured to generate a positive-logic output signal of the differential output signal, wherein the first subcircuit comprises one or more PMOS transistors configured to pull-up the positive-logic output signal for a first logic state of the differential output signal and one or more NMOS transistors configured to pull-down the positive-logic output signal for a second logic state opposite to the first logic state of the differential output signal;
- and
- wherein the second subcircuit is configured to generate a negative-logic output signal of the differential output signal, wherein the negative-logic output signal is inverted with respect to the positive-logic output signal, wherein the second subcircuit comprises one or more PMOS transistors configured to pull-up the negative-logic output signal for the second logic state of the differential output signal and one or more NMOS transistors configured to pull-down the negative-logic output signal for the first logic state of the differential output signal;
- and
- a control circuit configured to provide gate voltages of the PMOS transistors and/or the NMOS transistors of the output driver such that a relationship between an amount of on resistance of the PMOS transistors as compared to an amount of on resistance of the NMOS transistors is tunable.
3 more elements
A method of reducing electromagnetic interference, the method comprising:
- generating, using an output driver, a differential output signal comprising, wherein the output driver comprises a first subcircuit and a second subcircuit;
- generating, using the first subcircuit, a positive-logic output signal of the differential output signal, wherein the first subcircuit comprises one or more PMOS transistors configured to pull-up the positive-logic output signal for a first logic state of the differential output signal and one or more NMOS transistors configured to pull-down the positive-logic output signal for a second logic state opposite to the first logic state of the differential output signal;
- and
- generating, using the second subcircuit, a negative-logic output signal of the differential output signal, wherein the negative-logic output signal is inverted with respect to the positive-logic output signal, wherein the second subcircuit comprises one or more PMOS transistors configured to pull-up the negative-logic output signal for the second logic state of the differential output signal and one or more NMOS transistors configured to pull-down the negative-logic output signal for the first logic state of the differential output signal;
- and
- providing, using a control circuit, gate voltages of the PMOS transistors and/or the NMOS transistors of the output driver such that when switched on, a relationship between an amount of on resistance of the PMOS transistors as compared to an amount of on resistance of the NMOS transistors is tunable.
3 more elements
An apparatus for reducing electromagnetic interference, the apparatus comprising:
- means for generating a differential output signal comprising, wherein the output driver comprises a first subcircuit and a second subcircuit;
- means for generating, using the first subcircuit, a positive-logic output signal of the differential output signal, wherein the first subcircuit comprises one or more PMOS transistors configured to pull-up the positive-logic output signal for a first logic state of the differential output signal and one or more NMOS transistors configured to pull-down the positive-logic output signal for a second logic state opposite to the first logic state of the differential output signal;
- and
- means for generating a negative-logic output signal of the differential output signal, wherein the negative-logic output signal is inverted with respect to the positive-logic output signal, wherein the second subcircuit comprises one or more PMOS transistors configured to pull-up the negative-logic output signal for the second logic state of the differential output signal and one or more NMOS transistors configured to pull-down the negative-logic output signal for the first logic state of the differential output signal;
- and
- means for providing gate voltages of the PMOS transistors and/or the NMOS transistors of the output driver such that when switched on, a relationship between an amount of on resistance of the PMOS transistors as compared to an amount of on resistance of the NMOS transistors is tunable.
3 more elements
Dependencies are inferred from the claim text.