Planar compatible FDSOI design architecture
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSang Hoo Dhong, Jiann-Tyng Tzeng, Kushare Mangesh Babaji, Ramakrishnan Krishnan, Lee-Chung Lu, Ta-Pen Guo
Life of this patent
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Abstract
A multi-operation mode application specific integrated circuit (ASIC) implemented in fully-depleted silicon-on-insulator (FDSOI) includes an ASIC implemented in FDSOI having a plurality of operating modes, plurality of power rails, and a power supply that provides voltages for the first and second rails corresponding to the plurality of operating modes. The power rails include at least one VDD rail, at least one Vss rail, a first rail for biasing a NGP region of PMOS transistor devices in the ASIC, and a second rail for biasing a PGP region of NMOS transistor devices in the ASIC.
Claims20
A multi-operation mode application specific integrated circuit (ASIC) implemented in fully-depleted silicon-on-insulator (FDSOI), comprising:
- an ASIC implemented in FDSOI, the ASIC having a plurality of operating modes;
- a plurality of power rails comprising at least one VDD rail, at least one Vss rail, a first rail for biasing a N-top ground plane (NGP) region of PMOS transistor devices in the ASIC, and a second rail for biasing a P-top ground plane (PGP) region of NMOS transistor devices in the ASIC;
- and
- a power supply for providing voltages for the first and second rails corresponding to the plurality of operating modes.
A method of biasing a multi-operation mode application specific integrated circuit (ASIC) implemented in fully-depleted silicon-on-insulator (FDSOI):
- adaptively biasing a N-top ground plane (NGP) region of PMOS transistor devices in the ASIC and a P-top ground plane (PGP) region of NMOS transistor devices in the ASIC dependent on different operating modes of the ASIC, wherein in a first operating mode the NGP and PGP regions are biased to increase the threshold voltage of the NMOS and PMOS transistor devices and in a second operating mode the NGP and PGP regions are biased to lower the threshold voltage of the NMOS and PMOS transistor devices.
Dependencies are inferred from the claim text.