Secure design-for-test scan chains
AssigneeXilinx, Inc.
InventorsMatthew P. Baker, Weiguang Lu
Life of this patent
Estimating the term…
Abstract
A method of securing a design-for-test scan chain within a programmable integrated circuit device (IC) can include placing the programmable IC in an operational mode and responsive to a request to access a scan chain within the programmable IC, selectively enabling a secure mode within the programmable IC according to a configuration state of the programmable IC. Enabling secure mode within the programmable IC can provide access to the scan chain. Responsive to enabling the secure mode, the programmable IC can remain in the secure mode and be prevented from re-entering the operational mode until the programmable IC is power cycled.
Claims20
A method of securing a design-for-test scan chain within a programmable integrated circuit device (IC), the method comprising:
- placing the programmable IC in an operational mode;
- responsive to a request to access a scan chain within the programmable IC, selectively enabling a secure mode within the programmable IC according to a configuration state of the programmable IC, wherein enabling secure mode within the programmable IC provides access to the scan chain;
- and
- responsive to enabling the secure mode, retaining the programmable IC in the secure mode and preventing the programmable IC from re-entering the operational mode until the programmable IC is power cycled.
A method of securing a design-for-test scan chain within a programmable integrated circuit device (IC), the method comprising:
- placing the programmable IC in an operational mode;
- responsive to a request to access a scan chain within the programmable IC,
- determining a configuration state of the programmable IC;
- and
- selectively providing access to the scan chain through enablement of a secure mode within the programmable IC according to the configuration state of the programmable IC;
- responsive to determining that the programmable IC is configured, not enabling the secure mode and preventing access to the scan chain;
- and
- responsive to determining that the programmable IC is not configured, enabling the secure mode and allowing access to the scan chain.
A system for securing a design-for-test scan chain within a programmable integrated circuit (IC), the system comprising:
- a controller configured to receive a request for access to a scan chain while the programmable IC is in an operational mode, wherein the controller is configured to selectively enable a secure mode that provides access to the scan chain responsive to receiving the request according to a configuration state of the programmable IC, and wherein subsequent to the programmable IC entering the secure mode, the controller is configured to retain the programmable IC in the secure mode and prevent the programmable IC from re-entering the operational mode until the programmable IC is power cycled.
Dependencies are inferred from the claim text.