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US 8,437,217 B2Granted
Storing operational information in an array of memory cells
AssigneeMicron Technology, Inc.
InventorTheodore T. Pekny
Life of this patent
Estimating the term…
Abstract
The present disclosure includes methods, devices, modules, and systems for storing operational information in an array of memory cells. One method embodiment includes storing data units of operational information in memory cells of at least one row of a first block of memory cells. The method also includes using a column scramble to shift the order of the data units. The method includes storing the data units in memory cells of at least one row of a second block of memory cells, wherein an order of the data units stored in the at least one row of the second block is different than an order of the data units stored in memory cells of the at least one row of the first block.
Claims22
A method for storing operational information in an array of memory cells, the method comprising:
- storing operational information in a sequential order in successive memory cells of a first block, the sequential order beginning with a first memory cell coupled by a first sense line;
- storing the operational information in successive memory cells of a second block in the sequential order shifted such that the shifted sequential order begins with a second memory cell in the second block coupled by a second sense line, wherein the second block includes at least one memory cell coupled by the first sense line;
- sensing the first block and the second block;
- and
- leaving memory cells in pages not used for storing operational information in the first block and second block in an erased state.
2 more elements
A memory device, comprising:
- a first block of memory cells and a second block of memory cells dedicated to storing operational information;
- and
- control circuitry coupled to the first block and the second block and operable to:
- store the operational information in a sequential order in successive memory cells of a first block, the sequential order beginning with a first memory cell coupled by a first sense line;
- store the operational information in successive memory cells of the second block in the sequential order shifted such that the shifted sequential order begins with a second memory cell in the second block coupled by a second sense line, wherein the second block includes at least one memory cell coupled by the first sense line;
- sense the first block and the second block;
- and
- leave memory cells in pages not used for storing operational information in the first block and second block in an erased state.
5 more elements
A memory device, comprising:
- an array of memory cells, wherein a first number of memory cells constitute a page, and a second number of memory cells constitute a block;
- a first block and a second block dedicated to storing operational information;
- and
- control circuitry coupled to the array and operable to:
- store the operational information in a sequential order in successive memory cells of the first block, the sequential order beginning with a first memory cell coupled by a first sense line;
- store the operational information in successive memory cells of the second block in the sequential order shifted such that the shifted sequential order begins with a second memory cell in the second block coupled by a second sense line, wherein the second block includes at least one memory cell coupled by the first sense line;
- sense the first block and the second block;
- and
- sense the second block in response to a determination that the first block contains an error.
6 more elements
A memory device, comprising:
- a first block of memory cells and a second block of memory cells dedicated to storing operational information, wherein the operational information is selected from a group including:
- column redundancy data;
- block redundancy data;
- die identifiers;
- functionality trim data;
- bandgap data;
- and
- fuse trim data;
- and
- control circuitry coupled to the first block and the second block and operable to:
- store the operational information in a sequential order in successive memory cells of a first block, the sequential order beginning with a first memory cell coupled by a first sense line;
- store the operational information in successive memory cells of the second block in the sequential order shifted such that the shifted sequential order begins with a second memory cell in the second block coupled by a second sense line, wherein the second block includes at least one memory cell coupled by the first sense line;
- and
- sense the first block and the second block.
11 more elements
A memory device, comprising:
- a first block of memory cells and a second block of memory cells dedicated to storing operational information;
- and
- control circuitry coupled to the first block and the second block and operable to:
- store the operational information in a sequential order in successive memory cells of a first block, the sequential order beginning with a first memory cell coupled by a first sense line;
- store the operational information in successive memory cells of the second block in the sequential order shifted such that the shifted sequential order begins with a second memory cell in the second block coupled by a second sense line, wherein the second block includes at least one memory cell coupled by the first sense line;
- sense the first block and the second block;
- and
- sense the second block in response to a determination that the first block contains an error.
5 more elements
A memory device, comprising:
- a first block of memory cells and a second block of memory cells dedicated to storing operational information;
- and
- control circuitry coupled to the first block and the second block and operable to:
- store the operational information in a sequential order in successive memory cells of a first block, the sequential order beginning with a first memory cell coupled by a first sense line;
- store a copy of an inverse of the operational information stored in the first block in successive memory cells of the second block in the sequential order shifted such that the shifted sequential order begins with a second memory cell in the second block coupled by a second sense line, wherein the second block includes at least one memory cell coupled by the first sense line;
- and
- sense the first block and the second block.
4 more elements
Dependencies are inferred from the claim text.