US 8,432,751 B2 · Memory cell using BTI effects in high-k metal gate MOS

Abstract

Techniques and circuitry are disclosed for implementing non-volatile storage that exploit bias temperature instability (BTI) effects of high-k/metal-gate n-type or p-type metal oxide semiconductor (NMOS or PMOS) transistors. A programmed bitcell of, for example, a memory or programmable logic circuit exhibits a threshold voltage shift resulting from an applied programming bias used to program bitcells. In some cases, applying a first programming bias causes the device to have a first state, and applying a second programming bias causes the device to have a second state that is different than the first state. Programmed bitcells can be erased by applying an opposite polarity stress, and re-programmed through multiple cycles. The bitcell configuration can be used in conjunction with column/row select circuitry and/or readout circuitry, in accordance with some embodiments.

Claims20

Dependent claims

A storage device, comprising:

a first high-k oxide metal gate MOS transistor having its source tied to a sense node, and for providing a reference resistance of the device;
and
a second high-k oxide metal gate MOS transistor having a breakdown voltage and its drain tied to the sense node, and for providing a memory resistance of the device;
wherein the storage device is erasably programmable by applying a programming bias that is lower than the breakdown voltage to the gate of the second high-k oxide metal gate MOS transistor, thereby causing a sense node voltage level increase that can be detected during sensing.

1 more element

Dependencies are inferred from the claim text.

Memory cell using BTI effects in high-k metal gate MOS

Life of this patent

Memory cell using BTI effects in high-k metal gate MOS

Life of this patent

Abstract

Claims20