Thread count throttling for efficient resource utilization

A processor to perform graphics operations, the processor comprising:

• at least one execution unit for carrying out multiple threads of execution of graphics processing operations, wherein the at least one execution unit supports up to a maximum number of threads;
• wherein the processor interfaces with at least one memory device and supporting an allocation of thread-specific memory space in the at least one memory device, the allocation having a defined memory allocation size;
• wherein the processor responds to a command to limit the number of threads carried out by the at least one execution unit to a reduced number of threads of execution, the reduced number of threads of execution being less than the maximum number of threads of execution, the reduced number of threads of execution being determined based on the defined memory allocation size and a per thread memory requirement corresponding to the thread-specific memory space,
• wherein the thread-specific memory space comprises a plurality of blocks of memory, each block of memory being associated with a thread of execution, and wherein blocks of memory associated with threads belonging to a SIMD group are organized together within a contiguous addressing range in the thread-specific memory space,
• wherein the processor supports toggling of the at least one execution unit between a first mode of operation for carrying out the maximum number of threads of execution and a second mode of operation for carrying out the reduced number of threads of execution, and
• wherein in the first mode, the processor does not access the thread-specific memory space, and wherein in the second mode, the processor accesses the thread-specific memory space.

A processor to perform graphics operations, the processor comprising:

• at least one execution unit to carry out multiple threads of execution of graphics processing operations, wherein the at least one execution unit supports up to a maximum number of threads;
• wherein the processor interfaces with at least one memory device and supporting an allocation of thread-specific memory space in the at least one memory device, the allocation having a defined memory allocation size;
• wherein the processor responds to a command to limit the number of threads carried out by the at least one execution unit to a reduced number of threads of execution, the reduced number of threads of execution being less than the maximum number of threads of execution, the reduced number of threads of execution being determined based on the defined memory allocation size and a per thread memory requirement corresponding to the thread-specific memory space,
• wherein the processor supports toggling of the at least one execution unit between a first mode of operation for carrying out the maximum number of threads of execution and a second mode of operation for carrying out the reduced number of threads of execution, and
• wherein the processor supports dynamically toggling between the first mode and the second mode, without flushing existing threads of execution through a pipeline in the at least one execution unit before starting new threads of execution, and
• wherein in the first mode, the processor does not access the thread-specific memory space, and wherein in the second mode, the processor accesses the thread-specific memory space.