US 8,429,636 B2Granted

Handling dependency conditions between machine instructions

AssigneeOracle America, Inc.

InventorsYuan C. Chou, Jared C. Smolens, Jeffrey S. Brooks

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Abstract

Techniques for handling dependency conditions, including evil twin conditions, are disclosed herein. An instruction may designate a source register comprising two portions. The source register may be a double-precision register and its two portions may be single-precision portions, each specified as destinations by two other single-precision instructions. Execution of these two single-precision instructions, especially on a register renaming machine, may result in the appropriate values for the two portions of the source register being stored in different physical locations, which can complicate execution of an instruction stream. In response to detecting a potential dependency, one or more instructions may be inserted in an instruction stream to enable the appropriate values to be stored within one physical double precision register, eliminating an actual or potential evil twin dependency. Embodiments including a compiler that inserts instructions in a generated instruction stream to eliminate dependency conditions are also contemplated.

Claims18

Dependent claims

A non-transitory computer-readable storage medium having instructions stored thereon that are executable by a computing device to cause the computing device to perform operations comprising:

generating, from source code, a computer-executable instruction stream including a plurality of machine instructions, wherein said generating includes:
determining that a first machine instruction to be generated in the computer-executable instruction stream specifies a first portion of a logical register as a destination, wherein the logical register has at least the first portion and a second portion;
determining that a second, subsequent machine instruction to be generated in the computer-executable instruction stream specifies at least the first and second portions of the logical register as a source;
predicting that a dependency condition would exist between the first machine instruction and the second, subsequent machine instruction upon execution of the computer-executable instruction stream by a processor;
and
in response to the prediction that the dependency condition would exist between the first machine instruction and the second, subsequent machine instruction, inserting one or more machine instructions into the computer-executable instruction stream between the first machine instruction and the second, subsequent machine instruction;
wherein the inserted one or more machine instructions are executable by the processor to eliminate the dependency condition predicted to exist between the first machine instruction and the second, subsequent machine instruction.

4 more elements

A method, comprising:

generating, from source code, by a computer system including a host processor and a memory, a computer-executable instruction stream including a plurality of machine instructions executable by a target processor, wherein said generating includes:
determining that a first machine instruction to be generated in the computer-executable instruction stream specifies a first portion of a logical register as a destination, wherein the logical register has at least the first portion and a second portion;
determining that a second, subsequent machine instruction to be generated in the computer-executable instruction stream specifies at least the first and second portions of the logical register as a source;
predicting that a dependency condition would exist between the first machine instruction and the second, subsequent machine instruction upon execution of the computer-executable instruction stream by the target processor;
and
in response to the prediction that the dependency condition would exist between the first machine instruction and the second, subsequent machine instruction, inserting one or more machine instructions into the computer-executable instruction stream between the first machine instruction and the second, subsequent machine instruction;
wherein the inserted one or more machine instructions are executable by the target processor to eliminate the dependency condition predicted to exist between the first machine instruction and the second, subsequent machine instruction.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/173,415Filed 30 Jun 2011 · division
Priority: 22 Apr 2009
Published: US 2011/0258415 A120 Oct 2011
Granted: 23 Apr 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 9/3838
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: dependency mechanisms, e.g. register scoreboarding
G06F 9/30032
To perform operations on data operands: movement instructions, e.g. move, shift, rotate, shuffle
G06F 9/30109
Register structure: having multiple operands in a single register
G06F 9/384
Dependency mechanisms, e.g. register scoreboarding: register renaming

Family

Application12/428,459Parent of this division · filed 22 Apr 2009
US 2011/0258415 A1Pre-grant publication · published 20 Oct 2011
US 2010/0274992 A1Published application
US 8,458,444 B2Related patent
US 8,429,636 B2This patent

From the US filing history. Foreign family members aren’t listed.