Semiconductor integrated circuit
AssigneeRenesas Electronics Corporation
InventorsShuichi Kunie, Hiroki Machimura
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Abstract
An object of the present invention is to solve a problem that, if the state of a macro that is a debug target changes by a factor other than a debugger while the debugger debugs the macro as a target, the debugger becomes unable to continue debugging and the debugging terminates abnormally. In order to solve the aforementioned problem, disclosed is a semiconductor integrated circuit including a first register that stores a value indicating that the macro is in a reset state in response to a reset signal received during debugging of the macro, and a second register that stores a value indicating whether or not the macro has been in the reset state in the past by receiving a reset signal.
Claims12
A semiconductor integrated circuit comprising:
- a macro capable of transitioning to a predetermined state;
- a first register coupled to said macro to receive a predetermined signal to store a first value indicating whether or not said macro is in said predetermined state at a specific time point, and to store a second value indicating whether or not the macro is in the predetermined state at another specific time point which is after said specific time point;
- and
- a second register configured to store said first value based on the predetermined signal of said specific time point as a value indicating whether or not said macro has been in said predetermined state before said specific time point whereas the second register retains said stored first value and does not update said first value to said second value based on the predetermined signal of said another specific time point.
An integrated circuit comprising:
- a first register configured to receive a signal that causes the first register to store:
- a first value indicating whether a macro is in a first state at a first time;
- and
- a second value indicating whether the macro is in first state at a second time that is after the first time;
- and
- a second register configured to store a historical value indicating whether the macro was previously in the first state before the first time,
- wherein if the macro was previously in the first state, then the second register retains the historical value as the first value, otherwise the second register stores the historical value as a second value until the signal causes the first register to store the first value and then the second register retains the historical value as the first value.
Dependencies are inferred from the claim text.