Method of verifying logic circuit including decoders and apparatus for the same

A logic verification apparatus for verifying a logic circuit group including a decoder that decodes a selection signal and selects one signal line from a plurality of signal lines, the apparatus comprising:

• at least one processor;
• said processor executing a program read from a storage medium storing said program thereon, the program comprising:
• a signal line recognition unit that recognizes signal lines in the logic circuit based on design information regarding the logic circuit as a starting point;
• a decoder recognition unit that recognizes a circuit area including a logic element and an inverter as a decoder circuit area, the logic element and the inverter operating as an AND gate, the logic element and the inverter being able to output a signal having a logical value “1”, and determines a combination of logical values of selection signals inputted to the recognized decoder circuit area when a logical value of the starting point is logical value “1”;
• and
• a determination unit that determines whether a logical configuration of the recognized decoder circuit area is correct based on the number of the selection signals, and the combination of logical values of the selection signals, wherein the logical configuration of the recognized decoder circuit area is determined correct when the number of the selection signals inputted to the recognized decoder circuit area is the same as the number of bits of represented by the selection signal for selecting the signal line, and when all of the combination of logical values of the selection signals inputted to the decoder circuit areas are different from one another, each of the combination of logical values of the selection signals causing anyone of the decoder circuit area to output a signal having a logical value “1”.

A computer-readable recording medium storing a logic verification program for verifying a logic circuit group including a decoder that decodes a selection signal and selects one signal line of a plurality of signal lines, the program causing a computer to function as:

• a signal line recognition unit configured to recognize each of the signal lines in the circuit group based on design information regarding the circuit group;
• a decoder recognition unit configured to sequentially recognize logic elements located on an input side of the circuit group by using each of the recognized signal lines as a starting point based on the design information so as to recognize, as a decoder circuit area, an area including a logic element and inverter operating as an AND gate for outputting a signal having a logical value of “1”, and configured to determine a combination of logical values of the selection signals inputted to the decoder circuit area when a logical value of the signal line serving as the starting point is “1”;
• and
• a determination unit configured to determine whether a logical configuration of the decoder circuit area is correct based on the number of the selection signals inputted to the decoder circuit area and the combination of logical values of the selection signals, wherein the logical configuration of the recognized decoder circuit area is determined correct when the number of the selection signals inputted to the recognized decoder circuit area is the same as the number of bits of represented by the selection signal for selecting the signal line, and when all of the combination of logical values of the selection signals inputted to the decoder circuit areas are different from one another, each of the combination of logical values of the selection signals causing anyone of the decoder circuit area to output a signal having a logical value “1”.