Loading secure code into a memory
AssigneeSTMicroelectronics (Research & Development) Limited
InventorsDavid Smith, Andrew Marsh
Life of this patent
Estimating the term…
Abstract
A method of verifying the integrity of code in a programmable memory, the method including: receiving the code from an insecure memory; generating error detection bits for the code as it is received from the insecure memory; storing the code and the error detection bits in the programmable memory; and verifying the integrity of the code stored in the programmable memory by performing an authentication check on the code and the error detection bits stored in the programmable memory.
Claims39
A method of verifying integrity of code in a programmable memory, the method comprising:
- receiving the code from an insecure memory;
- generating error detection bits for the code received from the insecure memory;
- storing the code and the error detection bits in the programmable memory;
- verifying the integrity of the code stored in the programmable memory by performing an authentication check on the code and the error detection bits stored in the programmable memory;
- and
- if the integrity of the code is verified:
- fetching the code and the error detection bits from the programmable memory;
- determining whether the fetched error detection bits are correct for the fetched code;
- and
- if it is determined that the fetched error detection bits are correct, executing the fetched code.
A chip comprising:
- means for receiving code from an insecure memory;
- means for generating error detection bits for the code received from the insecure memory;
- a programmable memory for storing the code and the error detection bits;
- means for verifying the integrity of the code stored in the programmable memory by performing an authentication check on the code and the error detection bits stored in the programmable memory;
- means for fetching the code and the error detection bits from the programmable memory if the integrity of the code is verified;
- means for determining whether the fetched error detection bits are correct for the fetched code;
- and
- means for executing the fetched code if it is determined that the fetched error detection bits are correct.
A system comprising:
- a chip comprising:
- at least one first component for receiving code from an insecure memory;
- at least one second component for generating error detection bits for the code received from the insecure memory;
- a programmable memory for storing the code and the error detection bits;
- at least one third component for verifying the integrity of the code stored in the programmable memory by performing an authentication check on the code and the error detection bits stored in the programmable memory;
- and
- at least one processor for:
- when the integrity of the code has been verified, fetching the code and the error detection bits from the programmable memory;
- and
- when it is determined that the fetched error detection bits are correct, executing the fetched code.
A computer-readable storage medium encoded with computer-executable instructions for performing, when executed by at least one processor, a method of verifying integrity of code in a programmable memory, the method comprising:
- receiving the code from an insecure memory;
- generating error detection bits for the code received from the insecure memory;
- storing the code and the error detection bits in the programmable memory;
- verifying the integrity of the code stored in the programmable memory by performing an authentication check on the code and the error detection bits stored in the programmable memory;
- and
- if the integrity of the code is verified:
- fetching the code and the error detection bits from the programmable memory;
- determining whether the fetched error detection bits are correct for the fetched code;
- and
- if it is determined that the fetched error detection bits are correct, executing the fetched code.
Dependencies are inferred from the claim text.