Simplified parallel address-generation for interleaver
AssigneeLSI Corporation
InventorsShai Kalfon, Moshe Bukris
Life of this patent
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Abstract
An apparatus including a first circuit and a second circuit. The first circuit may be configured to store a block of data values arranged in a first order. The first circuit may be further configured to present a plurality of the data values in parallel in response to a plurality of address signals, where the data values are presented in a second order. The second circuit may be configured to generate the plurality of address signals in response to a first signal, a second signal and a third signal. The second circuit generally includes an even number of address generators configured to generate the plurality of address signals in parallel.
Claims20
An apparatus comprising:
- a first circuit configured to store a block of data values arranged in a first order, said first circuit further configured to present a plurality of said data values in parallel in response to a plurality of address signals, wherein said data values are presented in a second order;
- and
- a second circuit configured to generate said plurality of address signals in response to a first signal, a second signal and a third signal, said second circuit comprising an even number of address generators configured to generate said plurality of address signals in parallel, wherein each of said address generators is configured to generate a respective one of said plurality of address signals based upon a respective one of a plurality of bias signals.
An apparatus comprising:
- means for storing a block of data values arranged in a first order, said storage means further configured to present a plurality of said data values in parallel in response to a plurality of address signals, wherein said data values are presented in a second order;
- and
- means for generating said plurality of address signals in response to a first signal, a second signal and a third signal, wherein said generating means generates an even number of address signals in parallel and each of said even number of address signals is generated based upon a respective one of a plurality of bias signals.
A method for interleaving data values of a block of data, said method comprising the steps of:
- storing a data block to be interleaved in a storage medium;
- determining a first polynomial factor and a second polynomial factor based on a size of said data block;
- generating a plurality of bias values based on the first polynomial factor, the second polynomial factor, the size of said data block, and a number of address signals to be generated in parallel, wherein the number of address signals to be generated in parallel is even;
- generating the number of address signals in parallel based on said plurality of bias values, said first polynomial factor, said size of said data block, said number of address signals to be generated in parallel, and an index;
- and
- retrieving data values of said data block from said storage medium based on the address signals, wherein the data values are interleaved when retrieved.
Dependencies are inferred from the claim text.