Memory storage device, memory controller thereof, and method thereof for generating log likelihood ratio

A memory controller, comprising:

• a host system interface, for coupling to a host system;
• a memory interface, for coupling to a flash memory chip, wherein the flash memory chip comprises a plurality of memory cells, each of the memory cells has a plurality of storage states, and the storage states are distinguished by at least one bit data read voltage;
• a memory management circuit, coupled to the host system interface and the memory interface, for receiving a read instruction from the host system and obtaining a read data corresponding to the read instruction from the memory cells through the memory interface, wherein the read data is corresponding to a first storage state, the first storage state is one of the storage states, and the memory management circuit comprises a LLR lookup table;
• an ECC circuit, coupled to the memory management circuit, for performing an ECC procedure on the read data to obtain a second storage state corresponding to the read data when the read data is written, wherein the second storage state is one of the storage states;
• and
• a LLR estimation circuit, coupled to the memory management circuit and the ECC circuit, for obtaining an amount of storage error in the storage states satisfying a statistic number and executing a logarithmic operation according to the statistic number, an amount of the storage states, and the amount of storage error to generate a first LLR of the read data, wherein the storage error means that a corresponding data is in the second storage state when the data is written and is in the first storage state when the data is read.

A memory storage device, comprising:

• a connector, for coupling to a host system;
• a flash memory chip, comprising a plurality of memory cells, wherein each of the memory cells has a plurality of storage states, and the storage states are distinguished by at least one bit data read voltage;
• and
• a memory controller, coupled to the flash memory chip and the connector, comprising a LLR lookup table, wherein the memory controller controls the flash memory chip to obtain a read data from the memory cells by using the at least one bit data read voltage, wherein read data is corresponding to a first storage state, and the first storage state is one of the storage states, the memory controller also performs an ECC procedure on the read data to obtain a second storage state corresponding to the read data when the read data is written, wherein the second storage state is one of the storage states, the memory controller further obtains an amount of storage error in the storage states satisfying a statistic number, wherein the storage error means that a corresponding data is in the second storage state when the data is written and is in the first storage state when the data is read, and the memory controller executes a logarithmic operation according to the statistic number, an amount of the storage states, and the amount of storage error to generate a first LLR of the read data.