Dual ECC decoder

Abstract

A decoding apparatus includes a decoder and a control unit. The decoder includes circuitry that is configured to decode an Error Correction Code (ECC) by operating in one of a first operational mode having a first power consumption, and a second operational mode, in which at least part of the circuitry that is active during the first operational mode is deactivated and which has a second power consumption that is lower than the first power consumption. The control unit is configured to evaluate a criterion with respect to an input code word, to select one of the first and second operational modes responsively to the criterion, and to invoke the decoder to decode the input code word using the selected operational mode.

Dependencies are inferred from the claim text.