Memory device with internal signap processing unit

A method for data storage, comprising:

• storing data in a memory device comprising a plurality of analog memory cells that are fabricated on a first semiconductor die by writing first storage values to a group of the analog memory cells;
• after storing the data, reading from the memory cells in the group second storage values;
• performing a preprocessing operation on the read second storage values by processing circuitry that is fabricated on the first semiconductor die, so as to produce preprocessed data;
• providing the preprocessed data to a memory controller, which is fabricated on a second semiconductor die that is different from the first semiconductor die, so as to enable the memory controller to reconstruct the data responsively to the preprocessed data;
• accepting in the processing circuitry feedback from the memory controller regarding reconstruction of the data;
• and
• modifying the preprocessing operation of the processing circuitry responsively to the feedback;
• wherein the preprocessing operation comprises estimating a statistical property of the read second storage values and to provide the estimated statistical property to the memory controller;
• wherein the statistical property comprises one or more of:
• a mean of the read second storage values,
• a variance of the read second storage values,
• a number of the analog memory cells in the group whose read second storage values are within a given range of values,
• a Probability Density Function (PDF) of the second storage values,
• a histogram of the read second storage values,
• a Cumulative Distribution Function (CDF) of the read second storage values, and
• an inverse CDF of the second storage values.

A memory device, comprising:

• a first semiconductor die;
• a plurality of analog memory cells, which are fabricated on the first semiconductor die;
• and processing circuitry, which is fabricated on the first semiconductor die and is operative to store data in the plurality of the analog memory cells by writing input storage values to a group of the analog memory cells, to read, after storing the data, multiple output storage values from each of the analog memory cells in the group using respective, different threshold sets of read thresholds, thus providing multiple output sets of the output storage values corresponding respectively to the threshold sets, to preprocess the multiple output sets of the output storage values so as to produce preprocessed data, and to provide the preprocessed data to a memory controller that is fabricated on a second semiconductor die different from the first semiconductor die, so as to reconstruct the data stored in the group of the analog memory cells responsively to the preprocessed data;
• wherein the processing circuitry is operative to estimate a statistical property of the output storage values and to provide the estimated statistical property to the memory controller;
• wherein the statistical property comprises one or more of:
• a mean of the output storage values,
• a variance of the output storage values,
• a number of the analog memory cells in the group whose output storage values are within a given range of values,
• a Probability Density Function (PDF) of the output storage values,
• a histogram of the output storage values,
• a Cumulative Distribution Function (CDF) of the output storage values, and
• an inverse CDF of the output storage values.

A memory device, comprising:

• a first semiconductor die;
• a plurality of analog memory cells, which are fabricated on the first semiconductor die;
• and processing circuitry, which is fabricated on the first semiconductor die and is operative to store data in the plurality of analog memory cells by writing first storage values to a first group of the analog memory cells, to read from the memory cells in the first group, after storing the data, second storage values, at least some of which differ from the respective first storage values due to distortion, to receive from a memory controller, which is fabricated on a second semiconductor die different from the first semiconductor die, a request to cancel the distortion in the second storage values, to read responsively to the request third storage values from a second group of the analog memory cells, and to cancel the distortion in the second storage values based on the third storage values, so as to enable the memory controller to reconstruct the data;
• wherein the processing circuitry is operative to estimate a statistical property of the second storage values and to provide the estimated statistical property to the memory controller;
• wherein the statistical property comprises one or more of:
• a mean of the second storage values,
• a variance of the second storage values,
• a number of the analog memory cells in the group whose second storage values are within a given range of values,
• a Probability Density Function (PDF) of the second storage values,
• a histogram of the second storage values,
• a Cumulative Distribution Function (CDF) of the output storage values, and
• an inverse CDF of the second storage values.

A memory device, comprising:

• a first semiconductor die;
• a plurality of analog memory cells, which are fabricated on the first semiconductor die;
• and processing circuitry, which is fabricated on the first semiconductor die and is operative to store data in the plurality of analog memory cells by writing first storage values to a group of the analog memory cells, to read second storage values from the memory cells in the group after storing the data, to perform a preprocessing operation on the read second storage values so as to produce preprocessed data, to provide the preprocessed data to a memory controller fabricated on a second semiconductor die that is different from the first semiconductor die so as to enable the memory controller to reconstruct the data responsively to the preprocessed data, to accept feedback from the memory controller regarding reconstruction of the data, and to modify the preprocessing operation responsively to the feedback;
• wherein the processing circuitry is operative to estimate a statistical property of the second storage values and to provide the estimated statistical property to the memory controller;
• wherein the statistical property comprises one or more of:
• a mean of the second storage values,
• a variance of the second storage values,
• a number of the analog memory cells in the group whose second storage values are within a given range of values,
• a Probability Density Function (PDF) of the second storage values,
• a histogram of the second storage values,
• a Cumulative Distribution Function (CDF) of the second storage values, and
• an inverse CDF of the second storage values.

A data storage apparatus, comprising:

• a memory device, comprising:
• a plurality of analog memory cells;
• and processing circuitry, which is operative to store data by writing first storage values to a group of the analog memory cells, and to retrieve the data by reading second storage values from the analog memory cells in the group;
• and an auxiliary computation unit, which is coupled to preprocess the second storage values read from the analog memory cells to produce preprocessed data, wherein the processing circuitry is operative to receive, after storing the data, a request from a memory controller to retrieve the data, to read the second storage values from the memory cells in the group responsively to the request, to invoke the auxiliary computation unit to preprocess the read second storage values so as to produce the preprocessed data, and to provide the preprocessed data to the memory controller;
• wherein the processing circuitry is operative to estimate a statistical property of the second storage values and to provide the estimated statistical property to the memory controller;
• wherein the statistical property comprises one or more of:
• a mean of the second storage values,
• a variance of the second storage values,
• a number of the analog memory cells in the group whose second storage values are within a given range of values,
• a Probability Density Function (PDF) of the second storage values,
• a histogram of the second storage values,
• a Cumulative Distribution Function (CDF) of the second storage values, and
• an inverse CDF of the second storage values.

A memory device, comprising:

• a plurality of analog memory cells;
• and
• processing circuitry, which is operative to store data by writing first storage values to a group of the analog memory cells, to receive, after storing the data, a request from a memory controller to retrieve the data, to accept from the memory controller one or more analog control signals, which specify voltages or currents that are to be used by the processing circuitry in retrieving the data from the analog memory cells, to set the specified voltages or currents responsively to the request, to read from the memory cells in the group second storage values using the set voltages or currents, and to provide the second storage values to the memory controller;
• wherein the processing circuitry is operative to estimate a statistical property of the second storage values and to provide the estimated statistical property to the memory controller;
• wherein the statistical property comprises one or more of:
• a mean of the second storage values,
• a variance of the second storage values,
• a number of the analog memory cells in the group whose second storage values are within a given range of values,
• a Probability Density Function (PDF) of the second storage values,
• a histogram of the second storage values,
• a Cumulative Distribution Function (CDF) of the second storage values, and
• an inverse CDF of the second storage values.