Method and apparatus for detecting free page and a method and apparatus for decoding error correction code using the method and apparatus for detecting free page

A method of detecting a free page, the method comprising:

• inverting data read from a memory;
• detecting an amount of bits of inverted data having a logic value of 1 in an initially set data size unit;
• and
• determining before error correction code decoding is performed that a page read from the memory is a free page when the amount of bits is equal to or less than an initially set threshold value.

An apparatus for decoding an error correction code, the apparatus comprising:

• a first inverter that inverts data read from a memory;
• a free page detector that detects before error correction coding is performed an amount of bits having a logic value of 1 in an initially set data size unit from data output from the first inverter, and that generates a free page status signal when the amount of bits is equal to or less than an initially set threshold value;
• a data buffer that temporally stores the data read from the memory;
• a second inverter that inverts data read from the data buffer;
• and
• an error correction code decoder that detects an error based on an error correction code by inputting data output from the second inverter, that corrects a detected error and outputs a corrected error, and that, when the free page status signal is generated, stops detection and correction of the error.

An apparatus for decoding an error correction code, the apparatus comprising:

• a first inverter configured to invert 8-bit data read from a memory;
• a free page detector configured to detect an amount of bits having a logic value of 1 in an initially set data size unit from data output from the first inverter, and that generates a free page status signal when the amount of bits is less than or equal to an initially set threshold value;
• and
• an error correction code decoder configured to detect an error based on an error correction code by inputting data output from the first inverter, to stop correcting the error when the free page status signal is generated, and to correct the error when the free page status signal is not generated,
• wherein the free page detector comprises a logic circuit configured to count the amount of bits having a logic value 1 and output a counted number, the logic circuit comprising:
• a first full adder responsive to a first three bits of inverted 8-bit data;
• a second full adder responsive to a second three bits of inverted 8-bit data;
• a first half adder responsive to a last two bits of inverted 8-bit data;
• a third full adder responsive to a carry of each of the first full adder, the second full adder and the first half adder;
• a fourth full adder responsive to a sum of each of the first full adder, the second full adder and the first half adder;
• a second half adder responsive to a sum of each of the third full adder and the fourth full adder, and
• a third half adder responsive to a carry of each of the third full adder and the second half adder.