Edge-based decoders for low-density parity-check codes
AssigneeMarvell International Ltd.
InventorsNedeljko Varnica, Seo-How Low, Lingyan Sun, Zining Wu
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Abstract
Systems, methods, and apparatus are provided for increasing decoding throughput in an LDPC decoder, such as in a wireless communications receiver or in a data retrieval unit. A checker-board parity check matrix and edge-based LDPC decoder structure are provided in which both vertical and horizontal processors are used simultaneously. Horizontal processors may be grouped into type-A and type-B horizontal processors, and similarly, vertical processors may be grouped into type-A and type-B vertical processors. Type-A processors may be used in different clock cycles than type-B processors to update memory locations in a decoding matrix without causing memory access conflicts.
Claims18
A method comprising:
- receiving a codeword generated based on an LDPC code;
- determining soft information based on the received codeword;
- generating symbol node messages and parity check node messages based on the soft information;
- and
- iteratively processing the symbol node messages and the parity check node messages, wherein each iteration comprises:
- updating one or more symbol node messages in a first memory block simultaneously with updating one or more parity check node messages in a second memory block in a first time interval of the iteration,
- updating one or more symbol node messages in the second memory block simultaneously with updating one or more parity check node messages in the first memory block in a second time interval of the iteration occurring after the first time interval of the iteration, and
- updating, during a third time interval occurring after the first time interval and the second time interval, connector circulant messages in a connector circulant memory block located adjacent to the first memory block.
A system for decoding a LDPC codeword comprising:
- receiver circuitry configured to:
- obtain a received codeword generated based on an LDPC code;
- determine soft information based on the received codeword;
- and
- generate symbol node messages and parity check node messages based on the soft information;
- and
- a plurality of processors configured to:
- iteratively process the symbol node messages and the parity check node messages, wherein each iteration comprises:
- simultaneously updating one or more symbol node messages in a first memory block with one or more parity check node messages in a second memory block in a first time interval of the iteration;
- simultaneously updating one or more symbol node messages in the second memory block with one or more parity check node messages in the first memory block in a second time interval of the iteration occurring after the first time interval of the iteration, and
- updating, during a third time interval occurring after the first time interval and the second time interval, connector circulant messages in a connector circulant memory block located adjacent to the first memory block.
Apparatus for decoding a LDPC codeword comprising:
- means for obtaining a received codeword generated based on an LDPC code;
- means for determining soft information based on the received codeword;
- means for generating symbol node messages and parity check node messages based on the soft information;
- and
- means for iteratively processing the symbol node messages and the parity check node messages, wherein each iteration comprises:
- updating one or more symbol node messages in a first memory block simultaneously with updating one or more parity check node messages in a second memory block in a first time interval of the iteration,
- updating one or more symbol node messages in the second memory block simultaneously with updating one or more parity check node messages in the first memory block in a second time interval of the iteration occurring after the first time interval of the iteration, and
- updating, during a third time interval occurring after the first time interval and the second time interval, connector circulant messages in a connector circulant memory block located adjacent to the first memory block.
Dependencies are inferred from the claim text.