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AssigneeNational University Corporation Kyushu University Institute of Technology
InventorsKohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato
Estimating the term…
Provided are a generation device to reduce launch switching activity, yield loss risk, and power consumption of testing, even in the at-speed scan testing, even with a small number of don't-care (X) bits in input bits as in test compression, without any impact on test data volume, fault coverage, performance, and circuit design, by putting focus on internal lines in the circuit. The generation device includes a target internal line selection unit, a target internal line distinction unit, an identification unit that identifies a bit to be an unspecified bit and a bit to be a logic bit in the input bits, and an assignment unit that assigns a logic value 1 or a logic value 0 to unspecified bits in the input bits. The identification unit includes an unspecified bit identification unit and an input logic bit identification unit.
A generation device for generating a new set from a given set with fault model of the given set preserved or with fault coverage of the given set preserved or enhanced, the given set comprising input bits to be applied to a logic circuit being the target of fault detection, the given set being a test vector set consisting of test vectors whose input bits are logic bits of logic value 1 or 0, a test cube set consisting of test cubes whose input bits include one or more unspecified bits whose logic values are not specified, or a combination set consisting of both test vectors and test cubes, comprising:
A generation method for generating a new set from a given set with fault model of the given set preserved or with fault coverage of the given set preserved or enhanced, the given set comprising input bits to be applied to a logic circuit being the target of fault detection, the given set being a test vector set consisting of test vectors whose input bits are logic bits of logic value 1 or 0, a test cube set consisting of test cubes whose input bits include one or more unspecified bits whose logic values are not specified, or a combinational set consisting of both test vectors and test cubes, comprising the steps of:
A generation method, implemented in a computer, for generating a new set from a given set with fault model of the given set preserved or with fault coverage of the given set preserved or enhanced, the given set comprising input bits to be applied to a logic circuit being the target of fault detection, the given set being a test vector set consisting of test vectors whose input bits are logic bits of logic value 1 or 0, a test cube set consisting of test cubes whose input bits include one or more unspecified bits whose logic values are not specified, or a combinational set consisting of both test vectors and test cubes, comprising the steps of:
Dependencies are inferred from the claim text.
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Scanning methods, algorithms and patterns: data generators or compressors
Measuring electric variables
About 3 years 3 months of term left · ends 24 Jan 2030 (estimated)
The present invention relates to a generation device, a generation method, and a program, and particularly relates to a generation device, a generation method, and a program for testing a circuit such as a combinational circuit, a combinational portion of a full scan sequential circuit or the like.
As shown in FIG. 9, a semiconductor logic circuit is shipped through three stages, which are designing, manufacturing and testing stages. In the testing stage, a test vector, wherein the logic value of each logic bit is determined as either 0 or 1, is applied to the manufactured semiconductor logic circuit, and a test response from the semiconductor logic circuit is observed and compared to an expected test response, so that it is judged if the circuit is defective or defect-free. A ratio by which the defect-free products can be obtained is called the yield, and the yield largely affects the quality, reliability and manufacturing costs of the semiconductor logic circuit.
FIG. 10 illustrates a full scan sequential circuit of a common logic circuit.
FIG. 1 shows a schematic block diagram of a conversion device which can perform a test cube set generation method in accordance with an embodiment of the present invention.
FIG. 2 illustrates a specific behavior of the conversion device in accordance with FIG. 1.
FIG. 3 illustrates the basic idea of CTX.
FIG. 1 shows a schematic block diagram of a conversion device which can perform a test cube set generation method in accordance with an embodiment of the present invention.
Referring to FIG. 1, this conversion device 1 includes a target internal line selection unit 3 that selects a signal line in the logic circuit being the target of fault detection, a target internal line distinction unit 5 that distinguishes the selected signal lines in the logic circuit as described below, an identification unit 7 that identifies a bit which can be an unspecified bit and a bit which must remain as a logic bit in the input bits, and an assignment unit 9 that assigns a logic value 1 or a logic value 0 to unspecified bits in the input bits, the unspecified bits including an identified unspecified bit. The identification unit 7 includes an unspecified bit identification unit 11 and an input logic bit identification unit 13. The conversion device 1 with such a composition can convert an initial test vector set 15, which is an example of a given set to input bits, into a test cube set 17, which is an example of a new set. Further, the conversion device 1 can convert the test cube set 17 into a final test vector set 19 to generate a set to be applied into the logic circuit being the target of fault detection.
The examples of the target signal lines in the logic circuit selected by the target internal line selection unit 3 include a clock-control signal line connected into a clock-gating circuitry which can decide whether its downstream flip-flop group is activated or inactivated. The target internal line distinction unit 5 distinguishes the case such a clock-control signal line has a logic value 1 (0) from the case it has a logic value 0 (1). As an example, clock-control signal lines having logic value 1 are referred to as first target internal lines and clock-control signal lines having logic value 0 are referred to as second target internal lines. In addition, if an unspecified value (don't-care) is included in the given set, the target internal line identification unit 5 can further distinguish the clock-control signal lines having an unspecified value X as third target internal lines.