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US 8,429,470 B2Granted
Memory devices, testing systems and methods
AssigneeMicron Technology, Inc.
InventorMichael A. Shore
Life of this patent
Estimating the term…
Abstract
Testing systems and methods, as well as memory devices using such testing systems and methods, may facilitate testing of memory devices using a read-modify-write test procedure. One such testing system receives a signal indicative of at least some of a plurality of bits of data read from an address differing from each other, and then masks subsequent write operations at the same address. Therefore, any address at which the bits of read data do not all have the same value may be considered to be faulty. Failure data from the test can therefore be stored in the same array of memory cells that is being tested.
Claims28
A method of testing a memory device, comprising:
- writing first data to an array of memory cells in the memory device corresponding to each of a plurality of memory addresses in a first write operation;
- reading first read data from the array of memory cells in the memory device for each of the plurality of memory addresses in a first read operation;
- determining, based on the first react data, whether the first data were correctly stored in the array of memory cells corresponding to each of the plurality of memory addresses;
- writing second data, in a second write operation, to the memory cells in the memory device corresponding to each of the plurality of memory addresses that were determined to have correctly stored the first data;
- masking the second write operations to an address of the plurality of memory addresses in response to determining the address incorrectly stored the first data;
- reading second read data from the array of memory cells in the memory device corresponding to each of the plurality of memory addresses that were accessed in the second write operation;
- determining, based on the second read data, whether the second data were correctly stored in memory cells for each of the plurality of memory addresses that were accessed in the second write operation;
- writing third data, in a third write operation, to the array of memory cells in the memory device for each of the plurality of memory addresses that were determined to have correctly stored the second data;
- and
- reading third read data from the array of memory cells in the memory device corresponding to each of the plurality of memory addresses to determine which of the plurality of addresses may include a defect.
7 more elements
A method of testing a memory device comprising:
- writing first data to addresses in the memory device;
- and
- for each of the addresses in the memory device:
- reading read data stored at the address;
- determining whether the first data was correctly stored at the address based on the read data;
- masking subsequent write operations at the address in response to determining that the first data was incorrectly stored at the address;
- writing second data to the address, the writing of the second data being suppressed in response to the write operation was masked;
- and
- reading data from the addresses in the memory device to determine which of the addresses may include a defect.
6 more elements
A system for testing an array of memory cells, comprising:
- error detect circuitry configured to determine whether data read from the array of memory cells are in error and to generate an error signal responsive to detecting a read data error;
- and
- a write mask circuit coupled to receive the error signal from the error detect circuitry, the write mask circuit being configured to generate a write mask signal responsive to receiving the error signal indicating that the data read from the array of memory cells is in error.
A memory device, comprising:
- an array of memory cells;
- an addressing circuit coupled to the array of memory cells;
- a command decoder coupled to the array of memory cells;
- a data path coupling the array of memory cells and a plurality of data bus terminals;
- error detect circuitry coupled to the data path and being configured to determine whether data read from the array of memory cells are in error and to generate an error signal responsive to detecting a read data error;
- and
- a write mask circuit coupled to the data path and being configured to receive the error signal from the error detect circuitry, the write mask circuit being configured to mask write data from being coupled to the array of memory cells responsive to receiving the error signal indicating that the data read from the array of memory cells is in error.
4 more elements
Dependencies are inferred from the claim text.