Method and apparatus for transferring data between asynchronous clock domains

A memory controller capable of transferring data between asynchronous clock domains in relation to a phase shift relationship, the asynchronous clock domains including a source clock domain operating with a source clock signal and a receiving clock domain operating with a receiving clock signal, comprising:

• logic that determines the phase shift relationship between the source clock signal and a data strobe signal (DQS), wherein the DQS has a fixed relationship with the receiving clock signal;
• logic that transfers data between the source clock domain and the receiving clock domain using a small shift domain transfer logic when the phase shift relationship is below a predetermined threshold;
• and
• logic providing data, the source clock signal, and the receiving clock signal to a small shift domain transfer logic and a large shift domain transfer logic, wherein the small shift logic and the large shift logic provide for outputting a delayed data signal of a first delay and of a second delay, respectively;
• logic for providing the source clock signal and the DQS to a phase discriminator;
• logic for using the phase discriminator to compare the phase shift relationship with a predetermined threshold and select, via a transfer signal, if the phase relationship is less than a predetermined threshold, the small shift domain transfer logic or, if the phase relationship is greater than the predetermined threshold, the large domain transfer logic, to transfer data between the source clock domain and the receiving clock domain;
• and,
• logic that transfers the data between the source clock domain and the receiving clock domain using, if the small shift domain is selected, the small shift domain transfer logic and outputting the delayed data signal having the first delay;
• and
• logic that transfers the data between the source clock domain and the receiving clock domain using, if the large shift domain is selected, the large shift domain transfer logic and outputting the delayed data signal having the second delay being an additional half period of the source clock signal in comparison to the first delay;
• wherein the first and second delays are provided by the small and large domain transfer logics, respectively, to enable the data transfer to avoid timing problems that result in setup and hold violations and the outputted delayed data signal is a synchronized data signal for use by one or more devices in the receiving clock domain.