Dynamic tag allocation in a multithreaded out-of-order processor

An apparatus, comprising:

• a computer processor configured to execute instructions for a plurality of threads, wherein the processor includes a rename unit and a reorder buffer;
• wherein the reorder buffer comprises:
• a next tag array having first and second write ports, an output port, and a first read port;
• a reorder buffer array having a third write port and a second read port;
• a first buffer circuit that is configured to receive a first tag value from the rename unit and delay delivery of the first tag value to the first write port of the next tag array, wherein the second write port of the next tag array and the third write port of the reorder buffer array are configured to receive the first tag value from the rename unit at an earlier clock cycle of the computer processor than the first write port of the next tag array receives the first tag value from the first buffer circuit;
• and
• a second buffer circuit that is configured to receive a second tag value from the output port of the next tag array and provide the second tag value to the first read port of the next tag array and the second read port of the reorder buffer array;
• wherein the reorder buffer is configured to store execution information for instructions to be committed by the computer processor;
• wherein the reorder buffer is configured, in response to receiving a value indicating a tag value of a first plurality of instructions within a first thread, to generate a next tag value indicating a tag value of a second plurality of instructions within the first thread, wherein the second plurality of instructions are to be committed by the reorder buffer immediately after the first plurality of instructions.