Back to results
US 8,429,384 B2Granted
Interleaved hardware multithreading processor architecture
AssigneeHarman International Industries, Incorporated
InventorsJames D. Pennock, Ronald Baker, Brian R. Parker, Christopher Belcher
Life of this patent
Estimating the term…
Abstract
An architecture for a digital signal processor alleviates the difficulties and complexities normally associated with writing and optimizing programs to avoid stalls during which one instruction awaits the result of a prior instruction. The architecture coordinates the processing of data for multiple instructions through a multiple stage data pipeline. As a result, the architecture not only supports simultaneous execution of multiple programs, but also permits each program to execute without delays caused by inter-relationships between instructions within the program.
Claims31
A processor whose architecture comprises:
- an instruction data pipeline comprising multiple data pipeline stages, each data pipeline stage corresponding to a discrete set of processing for a program instruction, the multiple data pipeline stages connected in series to provide start to finish processing data for the program instruction by propagating instruction data corresponding to the program instruction through the multiple data pipeline stages of the instruction data pipeline;
- a digital signal processor (DSP) configured to sequentially load a first data pipeline stage of the instruction data pipeline with instruction data from program instructions in different programs from a set of multiple interleaved programs such that at any instant in time at least one of the multiple data pipeline stages is loaded with instruction data corresponding to another program instruction from one of the multiple interleaved programs and at least another one of the multiple data pipeline stages is loaded with instruction data corresponding to another program instruction from a different one of the multiple interleaved programs;
- and
- a machine state pipeline comprising multiple machine states, each machine state configured to store state data relating to a corresponding one of the multiple data pipeline stages, the machine state pipeline configured to propagate the state data for each of the multiple data pipeline stages sequentially through the multiple machine states in synchronism with the corresponding instruction data as it propagates through the data instruction pipeline such that the propagation of the instruction data and corresponding machine states through the data instruction pipeline and machine state pipeline results in the execution of one of the program instructions of one of the multiple interleaved programs.
1 more element
A method for processing data, the method comprising:
- sequentially loading a common instruction data pipeline in a processor with instruction data from program instructions in different programs from multiple interleaved programs, the common instruction data pipeline comprising multiple data pipeline stages, each data pipeline stage corresponding, to a discrete set of processing for the program instruction, the multiple data pipeline states connected in series to provide start to finish processing data for the program instruction;
- propagating the instruction data through the multiple serially coupled data pipeline stages of the common instruction data pipeline, such that at any instant in time, at least one of the multiple data pipeline stages is loaded with instruction data corresponding to a program instruction from one of the multiple interleaved programs and at least another one of the multiple data pipeline stages is loaded with instruction data corresponding to another program instruction from a different one of the multiple interleaved programs,
- propagating state data for the instruction data in each of the data pipeline stages through a machine state pipeline in the processor, the machine state pipeline comprising a series of machine states each corresponding to one of the data pipeline stages, where the state data is updated at each machine state according to the discrete set of processing at each corresponding data pipeline stage;
- and
- performing discrete set of processing at each data pipeline stage in context of the corresponding propagated state data.
2 more elements
Dependencies are inferred from the claim text.