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US 8,429,383 B2Granted
Multi-processor computing system having a JAVA stack machine and a RISC-based processor
AssigneeTexas Instruments Incorporated
InventorsGerard Chauvel, Serge Lasserre, Maija Kuusela, Dominique D'Inverno
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Abstract
A system comprises a first processor, a second processor coupled to the first processor, memory coupled to, and shared by, the first and second processors, and a synchronization unit coupled to the first and second processors. The second processor preferably comprises stack storage that resides in the core of the second processor. Further, the second processor executes stack-based instructions while the first processor executes one or more tasks including, for example, managing the memory via an operating system that executes only on the first processor. Associated methods are also disclosed.
Claims14
A system, comprising:
- a first processor;
- a second processor coupled to the first processor, the second processor having a core and comprising stack storage residing in the core;
- memory coupled to, and shared by, the first and second processors;
- and
- a synchronization unit coupled to the first and second processors, said synchronization unit synchronizes the execution of the first and second processors;
- wherein the second processor executes stack-based instructions while the first processor executes one or more tasks wherein the first processor manages the memory via an operating system that executes only on the first processor and the first processor executes a virtual machine that controls the execution of a program on the second processor;
- wherein the first processor executes a transaction targeting a pre-determined address and the synchronization unit detects said predetermined address and, as a result of detecting the pre-determined address, asserts a wait signal to cause said first processor to enter a reduced power or reduced performance mode;
- and
- wherein said second processor asserts a wait release signal that is received by said synchronization unit and that causes said synchronization unit to deassert said wait signal to the first processor.
6 more elements
A method, comprising:
- synchronizing the execution of first and second processors, the second processor having a core and comprising stack storage residing in the core, wherein synchronizing comprises detecting that the first processor is executing a transaction targeting a pre-determined address and, as a result of detecting that the pre-determined address is being targeted, asserting a wait signal to cause said first processor to enter a reduced power or reduced performance mode and synchronizing further comprises the second processor causing the wait signal to be de-asserted to terminate the first processor's reduced power or reduced performance mode;
- executing stack-based instructions in the second processor while the first processor executes one or more tasks;
- executing an operating system on the first processor and not on the second processor;
- executing a virtual machine on the first processor that controls the execution of a program on the second processor;
- and
- the first processor managing memory accessible to both the first and second processors via the operating system.
3 more elements
A system, comprising:
- a first processor;
- a second processor coupled to the first processor, the, second processor having a core and comprising stack storage residing in the core and having an internal data memory that holds a contiguous block of memory defined by an address stored in a register, and wherein local variables are stored in said data memory;
- memory coupled to, and shared by, the first and second processors;
- and
- a synchronization unit coupled to the first and second processors, wherein, based on a detection of a transaction to a predetermined address, said synchronization unit asserts a first signal to the first processor to cause the first processor to cease executing instructions and said synchronization unit receives a second signal from the second processor which thereby causes the synchronization unit to deassert the first signal;
- wherein the second processor executes stack-based instructions while the first processor executes one or more tasks wherein the first processor manages the memory via an operating system that executes only on the first processor and the first processor executes a virtual machine that controls the execution of a program on the second processor.
3 more elements
Dependencies are inferred from the claim text.