Optimizing TLB entries for mixed page size storage in contiguous memory

A system for accessing memory comprising:

• a processor device issuing a request for a memory page at a virtual address;
• a translation look-aside buffer (TLB) for storing one or more page table entries, wherein each of the one or more page table entries maps said virtual address to a physical address, and a table entry providing an exclusion bit indicating a memory sub-region to be excluded from within said requested memory page;
• a logic circuit for receiving a virtual address from said processor device, said logic circuit for matching the virtual address to a virtual page number in one of the page table entries to select the physical page number in the same page table entry,
• wherein said memory sub-region of the requested memory page is available for subsequent filling with one or more smaller fixed-size memory pages.