Semiconductor memory, memory system, and method of controlling the same
AssigneeSK hynix Inc.
InventorSang Sic Yoon
Life of this patent
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Abstract
Various embodiments of a semiconductor system, a semiconductor memory, and a method of controlling the same are disclosed. In one exemplary embodiment, the semiconductor memory may include a first circuit area configured to perform an operation corresponding to a general operation command and a second circuit area configured to provide the general operation command to the first circuit area. The second circuit area may be configured to determine whether the semiconductor memory is selected to perform the operation based on unique identification information and target identification information allocated to the semiconductor memory.
Claims13
A memory system comprising:
- a memory controller configured to generate an identification information store command, an identification information check command, a general operation command, an unique identification information, and a target identification information;
- and
- a plurality of semiconductor memories configured to store the unique identification information in response to the identification information store command and to select one or more of the plurality of semiconductor memories simultaneously based on the target identification information and the unique identification information in response to the identification information check command,
- wherein, the selected one or more of the plurality of semiconductor memories are configured to perform an operation corresponding to the general operation command,
- wherein each semiconductor memory of the plurality of semiconductor memories comprises:
- a first circuit area configured to perform the operation corresponding to the general operation command;
- and
- a second circuit area configured to store the unique identification information and provide the general operation command to the first circuit area depending on whether or not the semiconductor memory is selected.
A method of controlling a memory system comprising a plurality of semiconductor memories, the method comprising:
- generating an identification information store command and allocating unique identification information to the plurality of semiconductor memories;
- generating an identification information check command to select one or more of the plurality of semiconductor memories simultaneously;
- and
- generating a general operation command and providing the general operation command in common to the plurality of semiconductor memories, after generating the identification information check command,
- wherein each semiconductor memory of the plurality of semiconductor memories comprises:
- a first circuit area configured to perform the operation corresponding to the general operation command;
- and
- a second circuit area configured to store the unique identification information and provide the general operation command to the first circuit area depending on whether or not the semiconductor memory is selected.
A memory system comprising:
- a plurality of semiconductor memories configured to be allocated unique identification information and, wherein the selected one or more of the plurality of semiconductor memories are configured to perform an operation in response to a general operation command,
- wherein each semiconductor memory of the plurality of semiconductor memory comprises:
- a first circuit area configured to perform the operation corresponding to the general operation command;
- and
- a second circuit area configured to store the unique identification information and provide the general operation command to the first circuit area depending on whether or not the semiconductor memory is selected;
- and
- a memory controller configured to allocate the unique identification information to the plurality of semiconductor memories, to select the one or more of the plurality of semiconductor memories simultaneously, and to supply the general operation command to the plurality of semiconductor memories.
Dependencies are inferred from the claim text.