Back to results
US 8,429,367 B2Granted
Systems, methods and apparatuses for clock enable (CKE) coordination
AssigneeIntel Corporation
InventorsJames W. Alexander, Son H. Lam, Devadatta V. Bodas, Krishna Kant, Kai Cheng, Ian M. Steiner, Gopikrishna Jandhyala
Life of this patent
Estimating the term…
Abstract
Embodiments of the invention are generally directed to systems, methods, and apparatuses for clock enable (CKE) coordination. In some embodiments, a memory controller includes logic to predict whether a scheduled request will be issued to a rank. The memory controller may also include logic to predict whether a scheduled request will not be issued to the rank. In some embodiments, the clock enable (CKE) is asserted or de-asserted to a rank based, at least in part, on the predictions. Other embodiments are described and claimed.
Claims16
An integrated circuit comprising:
- scheduler logic to schedule a next request from pending requests for any one of a plurality of ranks of memory in a memory channel, each one of the plurality of ranks of memory representing a set of memory devices sharing a same chip select signal;
- clock enable (CKE) coordination logic to control a CKE signal to a rank of memory in coordination with the scheduler logic, the CKE coordination logic to:
- formulate a prediction as to whether the scheduler logic will or will not schedule the next request to the rank of memory, the prediction based on a combination of conditions that indicate the prediction is likely, the combination of conditions related to any two or more of:
- the other rank has reached its electrical throttling limit,
- the rank's minimum CKE delay has elapsed,
- thermal throttling is not de-asserting the rank's CKE,
- the scheduler logic has not shifted major mode since an immediately preceding scheduled request, and
- the other rank has a pending request of the same type;
- determine that the CKE signal to the rank of memory is de-asserted and assert the CKE signal to the rank of memory when the prediction is that the scheduler logic will schedule the next request to the rank of memory;
- and
- determine that the CKE signal to the rank of memory is asserted and de-assert the CKE signal to the rank of memory when the prediction is that the scheduler logic will not schedule the next request to the rank of memory.
8 more elements
A method comprising:
- scheduling a next request from pending requests for any one of a plurality of ranks of memory in a memory channel, each one of the plurality of ranks of memory representing a set of memory devices sharing a same chip select signal;
- coordinating a CKE signal to a rank of memory with the scheduling of the next request, wherein coordinating comprises:
- formulating a prediction as to whether the scheduling of the next request will or will not be to the rank of memory, the prediction based on a combination of conditions that indicate the prediction is likely, the combination of conditions related to any two or more of:
- the other rank has reached its electrical throttling limit,
- the rank's minimum CKE delay has elapsed,
- thermal throttling is not de-asserting the rank's CKE,
- the scheduling of the next request has not shifted major mode since an immediately preceding scheduled request, and
- the other rank has a pending request of the same type;
- determining that the CKE signal to the rank of memory is de-asserted and asserting the clock enable (CKE) signal to the rank of memory when the prediction is that the scheduling of the next request will be to the rank of memory;
- and
- determining that the CKE signal to the rank of memory is asserted and de-asserting the CKE signal to the rank of memory when the prediction is that the scheduling of the next request will not be to the rank of memory.
8 more elements
A system comprising:
- a memory channel including a plurality of ranks of memory, each one of the plurality of ranks of memory representing a set of memory devices sharing a same chip select signal;
- a request queue of pending requests for any one of the plurality of ranks of memory in the memory channel;
- a scheduler in communication with the request queue to schedule a next request from the pending requests for any one of the plurality of ranks of memory in the memory channel;
- a memory controller coupled with the memory channel and the scheduler, the memory controller including clock enable (CKE) coordination logic to control a CKE signal to a rank of memory in coordination with the scheduler, the CKE coordination logic to:
- formulate a prediction as to whether the scheduler will or will not schedule the next request to the rank of memory, the prediction based on a combination of conditions that indicate the prediction is likely, the combination of conditions related to any two or more of:
- the other rank has reached its electrical throttling limit,
- the rank's minimum CKE delay has elapsed,
- thermal throttling is not de-asserting the rank's CKE,
- the scheduler logic has not shifted major mode since an immediately preceding scheduled request, and
- the other rank has a pending request of the same type;
- determine that the CKE signal to the rank of memory is de-asserted and assert the CKE signal to the rank of memory when the prediction is that the scheduler will schedule the next request to the rank of memory;
- and
- determine that the CKE signal to the rank of memory is asserted and de-assert the CKE signal to the rank of memory when the prediction is that the scheduler will not schedule the next request to the rank of memory.
10 more elements
Dependencies are inferred from the claim text.