Information processor system
AssigneeRenesas Electronics Corporation
InventorSeiji Miura
Life of this patent
Estimating the term…
Abstract
In an information processor system including a memory device (MEM0), a memory control device (SL0) capable of controlling an operation of the memory device, and a plurality of bus masters (MS0 to MS3) capable of giving access to the memory device through the memory control device, the memory control device includes a control circuit (SDCON) capable of giving a notice of information about a time that a data transfer from the memory device can be started to the bus master related to an access request. The bus master can cause the time information thus given to be a judgment factor as to whether an access request is given to the memory device or not. Consequently, each of the bus masters can avoid the generation of a useless access request and a data transfer to the masters to be accessed can be carried out smoothly.
Claims4
An information processor system comprising:
- a memory device;
- a memory control device controlling an operation of the memory device;
- a plurality of bus masters each capable of giving access to the memory device through the memory control device;
- and
- an access arbitrating device capable of arbitrating a plurality of access requests from the plurality of bus masters,
- wherein the memory control device includes a buffer capable of accepting the plurality of access requests from the plurality of bus masters,
- wherein the memory control device transmits vacant information which indicates a vacant state of the buffer to the access arbitrating device when an access request can be accepted by the buffer, and in response the access arbitrating device transmits the access request to the memory control device,
- wherein the memory control device transmits time information to the access arbitrating device, the time information indicating a start time when a data transfer from the memory device or to the memory device will be started when the access request transmitted from the access arbitrating device is accepted by the buffer of the memory control device, and
- wherein the access arbitrating device transmits the time information to the bus master from which the access request issued.
Dependencies are inferred from the claim text.