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US 8,429,353 B2Granted
Distributed home-node hub
AssigneeOracle America, Inc.
InventorsRamaswamy Sivaramakrishnan, Stephen E. Phillips
Life of this patent
Estimating the term…
Abstract
A method and a system for processor nodes configurable to operate in various distributed shared memory topologies. The processor node may be coupled to a first local memory. The first processor node may include a first local arbiter, which may be configured to perform one or more of a memory node decode or a coherency check on the first local memory. The processor node may also include a switch coupled to the first local arbiter for enabling and/or disabling the first local arbiter. Thus one or more processor nodes may be coupled together in various distributed shared memory configurations, depending on the configuration of their respective switches.
Claims20
A processor system, comprising:
- a first local memory;
- a first processor node, wherein the first processor node is coupled to the first local memory, and wherein the first local memory is local to the first processor node, wherein the first processor node comprises:
- a first processor;
- and
- a first local arbiter, wherein the first local arbiter is configured to:
- in response to a memory conflict between a request for access to the first local memory and a request for access to the first local memory by one of other processor nodes, perform a coherency check on the first local memory, wherein the coherency check on the first local memory resolves the memory conflict for the first local memory in accordance with a coherency protocol;
- and
- a switch coupled to the first local arbiter for enabling or disabling the first local arbiter, wherein the switch is configured to turn the first local arbiter off for a central arbiter configuration in which a central arbiter maintains memory coherence of the first local memory and local memory of the other processor nodes, or on for a local arbiter configuration in which the first local arbiter maintains memory coherence of the first local memory and other local arbiters maintain memory coherence of the other processor nodes respectively.
5 more elements
A multi-core processor system, comprising:
- a plurality of local memories;
- a plurality of processor nodes, wherein each processor node is coupled to a respective one of the local memories, wherein each processor node comprises:
- a respective processor;
- and
- a respective local arbiter for controlling memory access;
- wherein the plurality of processor nodes comprises a first processor node having a first processor and a first local arbiter, and wherein the first processor and the first local arbiter are coupled to a first local memory of the plurality of local memories;
- and
- a first switch for enabling or disabling the first local arbiter, wherein the first switch is configured to turn the first local arbiter off for a central arbiter configuration in which a central arbiter maintains memory coherence of the plurality of local memories, or on for a local arbiter configuration in which the first local arbiter maintains memory coherence of the first local memory and other local arbiters maintain memory coherence of others of the plurality of processor nodes respectively in accordance with a coherency protocol, and wherein maintaining the memory coherence of the first local memory comprises:
- in response to a memory conflict between a request for access to the first local memory and a request for access to the first local memory by an other of the processor nodes, perform a coherency check on the first local memory, wherein the coherency check on the first local memory resolves the memory conflict for the first local memory in accordance with the coherency protocol.
6 more elements
A method for operating a multi-core processor system, the method comprising:
- assembling the multi-core processor system, wherein the multi-core processor system comprises:
- a plurality of local memories;
- a plurality of processor nodes, wherein each processor node is coupled to a respective one of the local memories, wherein each processor node comprises:
- a respective processor;
- and
- a respective local arbiter for controlling memory access;
- wherein the plurality of processor nodes comprises a first processor node having a first processor and a first local arbiter, and wherein the first processor and the first local arbiter are coupled to a first local memory of the plurality of local memories;
- configuring a first switch to either enable or disable the first local arbiter, wherein the first switch is configured to turn the first local arbiter off for a central arbiter configuration in which a central arbiter maintains memory coherence of the plurality of local memories, or on for a local arbiter configuration in which the first local arbiter maintains memory coherence of the first local memory and other local arbiters maintain memory coherence of others of the plurality of processor nodes respectively in accordance with a coherency protocol, and wherein maintaining the memory coherence of the first local memory comprises:
- in response to a memory conflict between a request for access to the first local memory and a request for access to the first local memory by an other of the processor nodes, perform a coherency check on the first local memory, wherein the coherency check on the first local memory resolves the memory conflict for the first local memory in accordance with the coherency protocol.
6 more elements
Dependencies are inferred from the claim text.