Techniques for cache injection in a processor system with replacement policy position modification
AssigneeInternational Business Machines Corporation
InventorsLakshminarayana Baba Arimilli, Ravi K. Arimilli, Balaram Sinharoy
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Abstract
A technique for performing cache injection includes monitoring, at a cache, addresses on a bus. Ownership of input/output data on the bus is then acquired by the cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache. A replacement policy position of the data block is then modified (to increase a probability that the data block is consumed prior to ejection from the cache).
Claims16
A method of performing cache injection, comprising:
- monitoring, at a cache, addresses on a bus in response to detection of a specific instruction sequence a determined number of times, wherein the specific instruction sequence includes two or more instructions;
- acquiring ownership of input/output data on the bus at the cache when an address on the bus, that is associated with the input/output data, corresponds to an address of a data block stored in the cache;
- and
- modifying a replacement policy position of the data block to increase a probability that the data block is consumed prior to ejection from the cache.
A cache system, comprising:
- a cache tag/data array;
- and
- a cache controller coupled to the cache tag/data array, wherein the cache controller is configured to:
- monitor addresses on a bus in response to detection of a specific instruction sequence a determined number of times, wherein the specific instruction sequence includes two or more instructions;
- acquire ownership of input/output data on the bus when an address on the bus, that is associated with the input/output data, corresponds to an address of a data block stored in the cache tag/data array;
- and
- modify a replacement policy position of the data block to increase a probability that the data block is consumed prior to ejection from the cache system.
A processor system, comprising:
- a processor;
- and
- a cache system coupled to the processor, wherein the cache system includes:
- a cache tag/data array;
- and
- a cache controller coupled to the cache tag/data array, wherein the cache controller is configured to:
- monitor addresses on a bus in response to detection of a specific instruction sequence a determined number of times, wherein the specific instruction sequence includes two or more instructions;
- acquire ownership of input/output data on the bus when an address on the bus, that is associated with the input/output data, corresponds to an address of a cache line stored in the cache tag/data array;
- and
- modify a replacement policy position of the cache line to increase a probability that the cache line is consumed prior to ejection from the cache system.
Dependencies are inferred from the claim text.