US 8,429,333 B2Granted

Memory system with efficient data search processing

AssigneeKabushiki Kaisha Toshiba

InventorsJunji Yano, Kosuke Hatsuda, Hidenori Matsuzaki

Life of this patent

Estimating the term…

Loading patent…

Abstract

A controller includes an identification information management table that manages identification information indicating, for each of addresses in second-management unit, whether one or more data in first management unit belonging to the addresses is stored in the second or the third storing area. When the controller executes a process of flushing data from the first storing area to the second storing area or the third storing area, the controller updates the identification information in the identification information management table. The controller executes a process of reading data from the second storing area or the third storing area by referring to the identification information. As a result, the speed of searches conducted in the management table is increased.

Claims20

Dependent claims

A memory system with efficient data search processing, the memory system comprising:

a nonvolatile semiconductor memory including a plurality of blocks, each one of the plurality of blocks being a unit of data erasing;
and
a controller configured to allocate at least one of the plurality of blocks in the nonvolatile semiconductor memory to first and second storing areas, wherein
the controller is further configured to:
in the first storing area, manage corresponding relationships between logical addresses and storage positions of data by a first management unit that is twice or larger a natural number times as large as a sector unit;
in the second storing area, manage corresponding relationships between logical addresses and storage positions of data in a second management unit that is twice or larger a natural number times as large as the first management unit;
and
execute data search processing by referring to identification information provided for each address aligned by the second management unit, the identification information indicating whether or not data in the first management unit belonging to a range of each address aligned by the second management unit is stored in the first storing area.

5 more elements

A method of controlling a memory system comprising:

storing data in a nonvolatile semiconductor memory including a plurality of blocks, each one of the plurality of blocks being a unit of data erasing;
allocating at least one of the plurality of blocks in the nonvolatile semiconductor memory to the first and second storing areas;
in the first storing area, managing corresponding relationships between logical addresses and storage positions of data by a first management unit that is twice or larger a natural number times as large as a sector unit;
in the second storing area, managing corresponding relationships between logical addresses and storage positions of data in a second management unit that is twice or larger a natural number times as large as the first management unit;
and
executing data search processing by referring to identification information provided for each address aligned by the second management unit, the identification information indicating whether or not data in the first management unit belonging to a range of the each address aligned by the second management unit is stored in the first storing area.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/394,582Filed 27 Feb 2009
Priority: JP 2008-0514821 Mar 2008
Published: US 2009/0222616 A13 Sep 2009
Granted: 23 Apr 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 12/0246
Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory: in block erasable memory, e.g. flash memory
G06F 12/0804
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: with main…
G06F 12/0866
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: for…
G06F 2212/7201
Details relating to flash memory management: logical to physical mapping or translation of blocks or pages