Serial interface NAND

A method of modifying internal data in a NAND memory device comprising:

• issuing a page read sequence from a host to an SPI controller to read data from a first address of a memory array of the NAND memory device and load the data into a specified cache address of the NAND memory device, wherein the page read sequence specifies the specified cache address of the NAND memory device;
• issuing a program load random data input sequence from the host to the SPI controller to load new data into one of a plurality of column addresses associated with the specified cache address of the NAND memory device, wherein the program load random data input sequence specifies the one of the plurality of column addresses;
• and
• issuing a program execute sequence from the host to the SPI controller to write data from the specified cache address of the NAND memory device to a second address of the memory array of the NAND memory device, wherein the program execute sequence specifies the second address of the memory array of the NAND memory device.

A method of caching data in a NAND memory device via an SPI interface comprising:

• loading first data to a specified cache address of the NAND memory device by issuing a first program load sequence that specifies the specified cache address to an SPI controller from a host;
• writing the first data from the specified cache address to a first address of a NAND memory array of the NAND memory device by issuing a first program execute sequence that specifies the first address of the NAND memory device to the SPI controller from the host;
• polling a status of the cache by issuing a first read status sequence to the SPI controller;
• if polling indicates that the cache is ready, then loading a portion of the specified cache address with second data by issuing a second program load sequence that specifies at least the portion of the specified cache address to the SPI controller from the host;
• polling the status of the cache and the NAND memory device by issuing a second read status sequence to the SPI controller;
• and
• if polling indicates that the cache is ready and the device is ready, writing the second data from the specified cache address to a second address of the NAND memory array of the NAND memory device by issuing a second program execute sequence that specifies the second address of the NAND memory device to the SPI controller from the host.