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US 8,429,319 B2Granted
Multi-port memory device with serial input/output interface
AssigneeHynix Semiconductor Inc.
InventorChang-Ho Do
Life of this patent
Estimating the term…
Abstract
A multi-port memory device includes a plurality of serial I/O data pads for providing a serial input/output (I/O) data communication; a plurality of ports for performing the serial I/O data communication with external devices through the serial I/O data pads; a plurality of banks for performing a parallel I/O data communication with the ports; a plurality of first data buses for transferring first signals from the ports to the banks; a plurality of second data buses for transferring second signals from the banks to the ports; and a switching unit for connecting the first data buses with the second data buses in response to a control signal.
Claims32
A multi-port memory device, comprising:
- a plurality of serial input/output (I/O) data pads;
- a plurality of ports for performing the serial I/O data communication with external devices through the serial I/O data pads;
- a plurality of banks for performing a parallel I/O data communication with the ports;
- a plurality of first data buses for receiving first signals outputted from the ports, and transferring the first signals to the banks;
- a plurality of second data buses for receiving second signals outputted from the banks, and transferring the second signals to the ports;
- a plurality of switching units for connecting the first data buses with the second data buses one to one in response to a mode enable signal, to transfer the first signals outputted from each of the plurality of ports to the same respective port of origin via the connected first and second data buses, or to transfer the first signals outputted from the ports to the banks via the first data buses;
- and
- a plurality of output drivers configured to interrupt the transferring of the second signals from the banks to the second data buses in response to the mode enable signal,
- wherein each of the output drivers includes:
- a first inverter for inverting a device enable signal for enabling the multi-port memory device;
- a first ate performing a NOR operation on an output of the first inverter and the mode enable signal;
- a second inverter for inverting an output of the first logic gate;
- a third inserter for inverting cell data outputted from a corresponding one of the banks;
- a second logic gate for performing an OR operation on outputs of the second and third inverters;
- a pull-up transistor having a gate receiving an output of the second logic gate and a source-drain path between a source voltage terminal and an output node;
- a third logic gate for performing an AND operation on outputs of the first logic gate and the third inverter;
- and
- a pull-down transistor having a gate receiving an output of the third logic gate and a source-drain path between a ground voltage terminal and the output node.
15 more elements
A multi-port memory device, comprising:
- a plurality of serial I/O data pads for providing a serial input/output (I/O) data communication;
- a test pad receiving a mode control signal;
- a plurality of ports for performing the serial I/O data communication with external devices through the serial I/O data pads;
- a plurality of banks for performing a parallel I/O data communication with the ports;
- a plurality of first data buses for receiving first signals outputted from the ports, and transferring the first signals to the banks;
- a plurality of second data buses for receiving second signals outputted from the banks, and transferring second signals to the ports;
- a test mode determination unit for generating a test mode enable signal in response to the mode control signal inputted through the test pad from an external device;
- a plurality of switching units for connecting the first data buses with the second data buses one to one in response to the test mode enable signal to transfer the first signals outputted from each of the plurality of ports to the same respective port of origin via the connected first and second data buses, or to transfer the first signals outputted from the ports to the banks via the first data buses;
- and
- a plurality of output drivers configured to intercept the transferring of the second signals from the banks to the second data buses in response to the test mode enable signal,
- wherein each of the output drivers includes:
- a first inverter for inverting a device enable signal for enabling the multi-port memory device;
- a first logic gate performing a NOR operation on an output of the first inverter and the test mode enable signal;
- a second inverter for inverting an output of the first logic gate;
- a third inverter for inverting cell data outputted from a corresponding one of the banks;
- a second logic gate for performing an OR operation on outputs of the second and third inverters;
- a pull-up transistor having a gate receiving an output of the second logic gate and a source-drain path between a source voltage terminal and an output node;
- a third logic rate for performing an AND operation on outputs of the first to and the third inverter;
- and
- a pull-down transistor having a gate receiving an output of the third logic gate and a source-drain path between a ground voltage terminal and the output node.
17 more elements
A multi-port memory device, comprising:
- a plurality of banks;
- a plurality of ports configured to perform a serial input/output(I/O) data communication with external devices and a parallel I/O data communication with the banks;
- a switching unit configured to transfer from each of the plurality of ports signals originally intended for the banks but redirected to the same respective port as originally transferred from, the signals being redirected back to the same respective port during a test mode for testing the plurality of ports without regard to the plurality of banks;
- and
- a plurality of output drivers configured to intercept a transferring of the banks to the ports during a test mode,
- wherein each of the output drivers includes:
- a first inverter for inventing a device enable signal for enabling the multi-port memory device;
- a first logic gate performing a NOR operation on an output of the first inverter and the test mode enable signal;
- a second inverter for inverting an output of the first logic gate;
- a third inverter for inverting cell data outputted from a corresponding one of the banks;
- a second logic gate for performing an OR operation on outputs of the second and third inverters;
- a pull-up transistor having a gate receiving an output of the second logic gate and a source-drain path between a source voltage terminal and an output node;
- a third logic gate for performing an AND operation on outputs of the first logic gate and the third inverter;
- and
- a pull-down transistor having a gate receiving an output of the third logic gate and a source-drain path between a ground voltage terminal and the output node.
12 more elements
Dependencies are inferred from the claim text.