Stashing system and method for the prevention of cache thrashing

In a system-on-chip (SoC) including a processor, a system for stashing packet information that prevents cache thrashing, the system comprising:

• an Ethernet subsystem having a network interface for accepting a plurality of packets, the Ethernet subsystem deriving a packet descriptor for each accepted packet, the Ethernet subsystem having an interface connected to an input/output (IO) bus to supply the packet descriptors and to supply the packets to an external memory;
• a queue subsystem including an ingress queue with a head connected to the IO bus, an egress queue having a head connected a tail of the ingress queue, and a queue manager (QM), the QM adding each packet descriptor to the ingress queue and transferring the packet descriptors from the ingress queue to the egress queue;
• a processor having an interface for accepting packet descriptors from a tail of the egress queue;
• a cache memory having an interface on the IO bus for storing packets;
• and,
• a context manager having a control interface connected to the QM, the context manager monitoring a fill level of packet descriptors in the egress queue and stashing packets from the external memory into cache in response to the fill level, where each stashed packet is associated with a packet descriptor in the egress queue.

In a system-on-chip (SoC) including a processor, a system for stashing packet information that prevents cache thrashing, the system comprising:

• a means for accepting a plurality of packets from a network interface, deriving a packet descriptor for each accepted packet, supplying the packet descriptors via an input/output (IO) bus, and supplying the packets to an external memory via the IO bus;
• a means for queuing including an ingress queue with a head connected to the IO bus, and an egress queue having a head connected a tail of the ingress queue, the queuing means adding each packet descriptor to the ingress queue and transferring the packet descriptors from the ingress queue to the egress queue;
• a means for processing having an interface for accepting packet descriptors from a tail of the egress queue;
• a means for caching having an interface on the IO bus for storing packets;
• and,
• a means for controlling cache stashing having a control interface connected to the queuing means, the cache stashing controlling means monitoring a fill level of packet descriptors in the egress queue and stashing packets from the external memory into cache in response to the fill level, where each stashed packet is associated with a packet descriptor in the egress queue.