Configurable ready/busy control
AssigneeSanDisk Technologies LLC
InventorsPeter Smith, Sergey Gorobets
Life of this patent
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Abstract
A memory unit has a busy control system that includes a busy control register that may be written by a controller. The contents of the busy control register determine whether a signal is sent from the memory unit to the controller and, if so, which of a plurality of signals is sent. A signal may automatically be sent from a selected memory unit and masked from an unselected unit.
Claims17
A memory unit in communication with a memory controller over a signal line in a memory system, comprising:
- a buffered array of non-volatile memory cells that includes a cache connected to the array of non-volatile memory cells;
- and
- a control circuit that selects an output signal from the memory unit from a plurality of signals according to data bits in a control register, the plurality of signals including a first signal indicating whether the buffered array is in a cache ready condition or a cache busy condition and a second signal indicating whether the buffered array is in an array ready condition or an array busy condition.
A memory system having a buffered non-volatile memory array in communication with a controller, comprising:
- a controller;
- an array of non-volatile memory cells;
- a cache connected to the array of non-volatile memory cells to hold data to be programmed to the array of non-volatile memory cells;
- and
- a ready/busy control circuit containing a control register, the ready/busy control circuit selecting an output signal to the controller from a plurality of signals including a first signal that indicates a ready/busy status of the array of non-volatile memory cells and a second signal that indicates a ready/busy status of the cache, the output signal selected according to the contents of the control register.
A memory system having a plurality of memory units in communication with a controller over a signal line, comprising:
- a controller;
- a plurality of memory units, an individual one of the plurality of memory units comprising a buffered array of non-volatile memory cells and a cache, a plurality of signals indicating conditions of the memory unit including at least array ready/busy and cache ready/busy, and a control register that selects an output signal to the controller from the plurality of signals.
Dependencies are inferred from the claim text.