Executing fixed point divide operations using a floating point multiply-add pipeline

A method, in a data processing system comprising a hardware implemented floating point execution unit, for executing a fixed point divide instruction using the floating point execution unit, comprising;

• receiving, in the floating point execution unit, operands of the fixed point divide instruction, wherein the operands include a numerator and a divisor;
• converting, in the floating point execution unit, the numerator and divisor to a floating point format;
• generating in the floating point execution unit an estimate of a reciprocal of the divisor;
• and
• determining a quotient for the fixed point divide instruction using the floating point formatted numerator, divisor and the estimate of the reciprocal of the divisor, wherein:
• generating an estimate of the reciprocal of the divisor includes using an estimate table unit in the floating point execution unit to lookup an estimate of the reciprocal of the divisor,
• the lookup of the estimate of the reciprocal of the divisor in the estimate table unit is based on a shifted mantissa of the divisor,
• determining a quotient for the fixed point divide instruction using the floating point formatted numerator, divisor and the estimate of the reciprocal of the divisor includes:
• determining if the divisor is associated with a special case for fixed point divide instructions;
• and
• ending the determination of the quotient for the fixed point divide instruction early if the divisor is associated with a special case for fixed point divide instructions, and wherein determining if the divisor is associated with a special case for fixed point divide instructions includes determining if the divisor is associated with one of when the divisor is a power of 2 or when the divisor is 1 or −1.

A system for executing a fixed point divide instruction using a floating point execution unit, comprising:

• one or more floating point registers;
• and
• a floating point execution unit coupled to the floating point registers, wherein the floating point execution unit receives operands of the fixed point divide instruction from the one or more floating point registers, wherein the operands include a numerator and a divisor, converts the numerator and divisor to a floating point format, generates an estimate of a reciprocal of the divisor, and determines a quotient for the fixed point divide instruction using the floating point formatted numerator, divisor and the estimate of the reciprocal of the divisor, wherein the floating point unit includes an estimate table unit, and wherein the floating point execution unit generates an estimate of the reciprocal of the divisor using the estimate table unit to lookup an estimate of the reciprocal of the divisor based on a shifted mantissa of the divisor, wherein the floating point execution unit determines a quotient for the fixed point divide instruction includes:
• making multiple passes through a pipeline of the floating point execution unit using results from a previous pass through the pipeline of the floating point execution unit, to generate estimates of the quotient for the fixed point divide instruction wherein a final pass through the pipeline of the floating point execution unit involves truncating an estimate of the quotient to generate a final estimate of the quotient for the fixed point divide instruction.