Method of forcing 1's and inverting sum in an adder without incurring timing delay

An adder comprising:

• a first half-sum generator that generates a first half-sum output based on a carry bit of zero and based on two or more control signals which indicate that a result of the adder should be manipulated;
• a second half-sum generator that generates a second half-sum output based on a carry bit of one and based on the control signals;
• first sum completion logic that combines a first carry bit with the first half-sum output to produce a first set of sum bits;
• second sum completion logic that combines a second carry bit with the second half-sum output to produce a second set of sum bits;
• and
• a multiplexer which selects between the first and second sets of sum bits based on a true carry signal.

An adder comprising:

• first half-sum generator means for generating a first half-sum output based on a carry bit of zero and based on two or more control signals which indicate that a result of the adder should be manipulated;
• second half-sum generator means for generating a second half-sum output based on a carry bit of one and based on the control signals;
• first sum completion means for combining a first carry bit with the first half-sum output to produce a first set of sum bits;
• second sum completion means for combining a second carry bit with the second half-sum output to produce a second set of sum bits;
• and
• multiplexer means for selecting between the first and second sets of sum bits based on a true carry signal.