System for address-event-representation network simulation

A method for address-event-representation network simulation, comprising:

• receiving an input message at a source table of a node in a hardware structure comprised of a plurality of interconnected processing modules configured to simulate a plurality of interconnected nodes;
• identifying a weight associated with a source of the input message, the identified weight located in the source table;
• updating a node state as a function of the identified weight, the updating performed by state management logic;
• generating an output signal responsive to the updated node state;
• accessing a target table to identify a target to receive an output message;
• and
• generating the output message in response to the output signal.

A design structure tangibly embodied in a non-transitory machine-readable data storage medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• a hardware structure comprised of a plurality of interconnected processing modules configured to simulate a plurality of interconnected nodes, wherein each node comprises:
• a source table configured to receive an input message and identify a weight associated with a source of the input message;
• state management logic configured to update a node state as a function of the identified weight, and generate an output signal responsive to the updated node state;
• and
• a target table configured to generate an output message in response to the output signal, identify a target to receive the output message, and transmit the output message.